ISL62776IRTZ datasheet(30/50 Pages) RENESAS

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ISL62776

5. AMD Serial VID Interface 2.0

R16DS0044EU0200 Rev.2.00

Page 30 of 49

Oct.8.20

5.6

Power States

SVI 2.0 defines two power state indicator levels, PSI0_L and PSI1L. See Table 7 for information about these

power state indicators. As processor current consumption is reduced, the power state indicator level changes to

improve VR efficiency under low power conditions.

When the Core VR is operating in 3-phase mode and PSI0_L is asserted, Channels 2 and 3 are tri-stated and

Channel 1 remains active in CCM mode. When PSI1_L is asserted, Channel 1 enters into enters Diode Emulation

Mode (DEM) to boost efficiency.

When PSI0_L is asserted for the SOC VR, the SOC regulator remains in Continuous Conduction Mode (CCM).

When PSI1_L is asserted, the SOC VR transitions to DEM to boost efficiency.

The processor can assert or deassert PSI0_L and PSI1_L out of order. PSI0_L takes priority over PSI1_L. If

PSI0_L is deasserted while PSI1_L is still asserted, the ISL62776 returns the selected VR back to full channel

CCM operation.

5.7

Dynamic Load Line Slope Trim

The ISL62776 supports the SVI 2.0 ability for the processor to manipulate the load line slope of the Core and

SOC VRs independently using the serial VID interface. The slope manipulation applies to the initial load line

slope. A load line slope trim typically coincides with a VOTF change. See Table 8 for more information about the

load line slope trim feature.

Table 6.

SVD Data Packet

Bits

Description

1:5

Always 11000b

Core domain selector bit. If set, the following data byte contains the VID, power state, telemetry control, load line trim, and

offset trim to apply to the Core VR.

SOC domain selector bit. If set, the following data byte contains the VID, power state, telemetry control, load line trim, and

offset trim to apply to the SOC VR.

Always 0b

ACK bit

PSI0_L

11:17

VID code bits [7:1]

ACK bit

VID code bit [0]

PSI1_L

TFN (Telemetry Functionality)

22:24

Load line slope trim

25:26

Offset trim [1:0]

ACK bit

Table 7.

PSI0_L and PSI1_L Definition

Function

Bit

Description

PSI0_L

Power State Indicate Level 0. When this signal is asserted (active Low), the processor is in a low

enough power state for the ISL62776 to boost efficiency by dropping phases and entering 1-Phase

CCM.

PSI1_L

Power State Indicate Level 1. When this signal is asserted (active Low), the processor is in a low

enough power state for the ISL62776 to boost efficiency by dropping phases and entering 1-Phase

DEM.

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