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ISL62776IRTZ Datasheet(PDF) 33 Page - Renesas Technology Corp

Part # ISL62776IRTZ
Description  Multiphase PWM Regulator for AMD CPUs Using SVI2
PDF  50 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL62776IRTZ Datasheet(HTML) 33 Page - Renesas Technology Corp

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ISL62776
7. Protection Features
R16DS0044EU0200 Rev.2.00
Page 33 of 49
Oct.8.20
7.
Protection Features
The Core VR and SOC VR both provide overcurrent, current-balance, undervoltage, and overvoltage fault
protections. The controller provides over-temperature protection.
7.1
Overcurrent
You can use the IMON voltage to determine the load current at any moment in time. The Overcurrent Protection
(OCP) circuitry monitors the IMON voltage to determine when a fault occurs. Based on the description in Voltage
Regulation and Load Line Implementation, the current that flows out of the IMON pin is proportional to the Isum
current. The Isum current is created from the sensed voltage across Cn, which is a measure of the load current
based upon the sensing element selected. The IMON current is generated internally and is 1/4 of the Isum current.
The EDC or IDDspike current value for the AMD CPU load sets the maximum current level for droop and the
IMON voltage of 1.2V, which indicates 100% loading for telemetry. The Isum current level at maximum load, or
IDDspike, is 36µA, which translates to an IMON current level of 9µA. The IMON resistor is 133kΩ and the 9µA
flowing through the IMON resistor results in a 1.2V level at maximum loading of the VR.
The overcurrent threshold is 1.5V on the IMON pin. Based on a 1.2V IMON voltage equating to 100% loading, the
additional 0.3V provided above this level equates to a 25% increase in load current before an OCP fault is
detected. The EDC or IDDspike current is sets the 1.2V on IMON for full load current, so the OCP level is
1.25 times the EDC or IDDspike current level. This additional margin above the EDC or IDDspike current allows
the AMD CPU to enter and exit the IDDspike performance mode without issue unless the load current is out of line
with the IDDspike expectation, thus the need for overcurrent protection.
When the voltage on the IMON pin meets the overcurrent threshold of 1.5V, an OCP event occurs. Within 2µs of
detecting an OCP event, the controller asserts VR_HOT_L low to communicate to the AMD CPU to throttle back.
A fault timer begins counting while IMON is at or above the 1.5V threshold. The fault timer lasts 7.5µs to 11µs,
then flags an OCP fault. The controller then tri-states the active channels and goes into shutdown. PGOOD goes
low and a fault flag from this VR is sent to the other VR, which is shut down within 10µs. If the IMON voltage drops
below the 1.5V threshold before the fault timer count finishes, the fault timer is cleared and VR_HOT_L is taken
high.
The ISL62776 also features a Way-Overcurrent (WOC) feature that immediately takes the controller into
shutdown. This protection is also referred to as fast overcurrent protection for short-circuit protection. If the IMON
current reaches 15µA, WOC is triggered, active channels are tri-stated, the controller is placed in shutdown, and
PGOOD is pulled low. There is no fault timer on the WOC fault; the controller takes immediate action. The other
controller output is also shut down within 10µs.
7.2
Current Balance
The controller monitors the ISENx pin voltages to determine current balance protection. If the ISENx pin voltage
difference is greater than 9mV for 1ms, the controller declares a fault and latches off.
7.3
Undervoltage
If the VSEN pin voltage falls below the output voltage VID value plus any programmed offsets by -325mV, the
controller declares an undervoltage fault. The controller deasserts PGOOD and tri-states the power MOSFETs.
7.4
Overvoltage
If the VSEN pin voltage exceeds the output voltage VID value plus any programmed offsets by +325mV, the
controller declares an overvoltage fault. The controller deasserts PGOOD and turns on the low-side power
MOSFETs. The low-side power MOSFETs remain on until the output voltage is pulled down below the VID set
value. When the output voltage is below this level, the lower gate is tri-stated. If the output voltage rises above the
overvoltage threshold again, the protection process is repeated. This behavior provides the maximum amount of
protection against shorted high-side power MOSFETs while preventing output ringing below ground.



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