ISL62776IRTZ datasheet(13/50 Pages) RENESAS

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ISL62776

3. Theory of Operation

R16DS0044EU0200 Rev.2.00

Page 13 of 49

Oct.8.20

Theory of Operation

3.1

Multiphase R3 Modulator

The ISL62776 is a multiphase regulator that implements two voltage regulators, Core VR and SOC VR, on one

chip controlled by AMD’s SVI 2.0 protocol. The Core VR can be programmed for 1-, 2-, 3-, or 4-phase operation.

The SOC VR is a 1-phase regulator. Both regulators use the Renesas proprietary R3 (Robust Ripple Regulator)

modulator. The R3 modulator combines the best features of PWM, such as fixed frequency and hysteretic, and

eliminates many of its shortcomings. Figure 6 conceptually shows the multiphase R3 modulator circuit and Figure 7

shows the operational principles.

Inside the IC, the modulator uses the master clock circuit to generate the clocks for slave circuits. The modulator

discharges the ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor. The Crm

voltage, VCRM, is a sawtooth waveform traversing between the VW and COMP voltages. The Crm voltage resets

to VW when it reaches COMP and generates a one-shot master clock signal. A phase sequencer distributes the

master clock signal to the slave circuits.

• If the Core VR is in 3-phase mode, the master clock signal is distributed to the three phases and the Clock1

through Clock3 signals are 120 degrees out-of-phase

• If the Core VR is in 2-phase mode, the master clock signal is distributed to Phases 1 and 2 and the Clock1 and

Clock2 signals are 180 degrees out-of-phase

• If the Core VR is in 1-phase mode, the master clock signal is distributed to Phase 1 only and is the Clock1

signal

Figure 6. R3 Modulator Circuit

ISL62776IRTZ Datasheet(PDF) 13 Page - Renesas Technology Corp