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MPC855T Datasheet(PDF) 58 Page - NXP Semiconductors |
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MPC855T Datasheet(HTML) 58 Page - NXP Semiconductors |
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58 / 77 page  MPC860 PowerQUICC Family Hardware Specifications, Rev. 10 58 Freescale Semiconductor CPM Electrical Characteristics Figure 59. Ethernet Collision Timing Diagram Figure 60. Ethernet Receive Timing Diagram 135 RSTRT active delay (from TCLK1 falling edge) 10 50 ns 136 RSTRT inactive delay (from TCLK1 falling edge) 10 50 ns 137 REJECT width low 1 — CLK 138 CLKO1 low to SDACK asserted2 —20 ns 139 CLKO1 low to SDACK negated2 —20 ns 1 The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2/1. 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. Table 22. Ethernet Timing (continued) Num Characteristic All Frequencies Unit Min Max CLSN(CTS1) 120 (Input) RCLK1 121 RxD1 (Input) 121 RENA(CD1) (Input) 125 124 123 127 126 Last Bit |
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