MPC855T datasheet(69/77 Pages) NXP

69 / 77 page

MPC860 PowerQUICC Family Hardware Specifications, Rev. 10

Freescale Semiconductor

FEC Electrical Characteristics

13.3

MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 31 provides information on the MII async inputs signal timing.

Figure 74 shows the MII asynchronous inputs signal timing diagram.

Figure 74. MII Async Inputs Timing Diagram

13.4

MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 32 provides information on the MII serial management channel signal timing. The FEC functions

correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under

investigation.

Table 31. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK

period

Table 32. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum propagation

delay)

0—

M11

MII_MDC falling edge to MII_MDIO output valid (max prop delay)

—

M12

MII_MDIO (input) to MII_MDC rising edge setup

—

M13

MII_MDIO (input) to MII_MDC rising edge hold

—

M14

MII_MDC pulse width high

40%

60%

MII_MDC

period

M15

MII_MDC pulse width low

40%

60%

MII_MDC

period

MII_CRS, MII_COL

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