ATECC608A datasheet(59/81 Pages) MICROCHIP

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I2C Interface

The I2C Interface uses the SDA and SCL pins to indicate various I/O states to the ATECC608A-TNGLoRaWAN. This

interface is designed to be compatible at the protocol level with the Microchip AT24C16 Serial EEPROM operating at

1 MHz.

Note: There are many differences between the two devices (for example, the ATECC608A-TNGLoRaWAN and

AT24C16 have different default I2C addresses); therefore, designers should read the respective data sheets carefully.

The SDA pin is normally pulled high with an external pull-up resistor because the ATECC608A-TNGLoRaWAN

includes only an open-drain driver on its output pin. The bus master may either be open-drain or totem pole. In the

latter case, it should be tri-stated when the ATECC608A-TNGLoRaWAN is driving results on the bus. The SCL pin is

an input and must be driven both high and low at all times by an external device or resistor.

7.1

I/O Conditions

The device responds to the following I/O conditions:

7.1.1

Device is Asleep

When the device is asleep, it ignores all but the Wake condition.

• Wake - Upon the rising edge of SDA, after SDA has been held low for a period ≥ tWLO, the device exits the Low-

Power mode. After a delay of tWHI, it will be ready to receive I2C commands.

• The device ignores any levels or transitions on the SCL pin when the device is idle or asleep and during tWLO. At

some point during tWHI, the SCL pin is enabled and the conditions listed in Section 7.1.2 Device is Awake are

honored.

The Wake condition requires that either the system processor manually drives the SDA pin low for tWLO, or a data

byte of 0x00 be transmitted at a clock rate sufficiently slow so that SDA is low for a minimum period of tWLO. When

the device is awake, the normal processor I2C hardware and/or software can be used for device communications.

This includes the I/O sequences required to put the device back into Low-Power (i.e., Sleep) mode.

Tip: A simple way to generate a wake pulse is to send a byte of 0x00 at 100 kHz. Subsequent commands

can be run at a higher frequency.

In the I2C mode, the device will ignore a wake sequence that is sent when the device is already awake.

Multiple Devices on the Bus

When there are multiple devices on the bus and the I2C interface is run at speeds of less than ~300 kHz1, the

transmission of certain data patterns will cause the ATECC608A-TNGLoRaWAN devices on the bus to wake up. The

lower the frequency the higher the probability that the device wakes up. Because subsequent device addresses

transmitted along the bus only match the desired devices, the ATECC608A-TNGLoRaWAN will not respond but will

be awake. It is recommended that after communicating with another device at slow frequencies, a sleep or idle

sequence be issued to place the ATECC608A-TNGLoRaWAN back into a known state.

Important: tWLO is the minimum time that the system must provide to ensure that the ATECC608A-

TNGLoRaWAN will wake under all manufacturing and environmental conditions. In actuality, the device

may wake up with a lesser pulse width.

1 The actual frequency for a given device will vary with process and environmental factors. This value is

considered safe under all conditions.

ATECC608A-TNGLoRaWAN

I2C Interface

Complete Datasheet

DS40002154B-page 59

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