MCP3465R datasheet(41/110 Pages) MICROCHIP

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DS20006414C-page 41

MCP3465R

FIGURE 5-3:

MDAT Serial Outputs

Depending on the Modulator Output Code.

5.4.3

BOOST MODES

The Delta-Sigma modulator includes a programmable

biasing circuit in order to further adjust the power

consumption to the sampling speed applied through

the MCLK. This can be programmed through the

BOOST[1:0] bits in the CONFIG2 register. The

different BOOST settings are applied to the entire

modulator circuit, including the voltage reference

buffers. The settings of the BOOST[1:0] bits are

described in Table 5-5.

The maximum achievable Analog Master Clock

(AMCLK) speed, the maximum sampling frequency

(DMCLK) and the maximum achievable data rate

(DRCLK) are highly dependent on the BOOST[1:0] and

GAIN[2:0] bits setting. A higher BOOST setting allows

the circuit’s bandwidth to be increased and allows a

higher analog master clock rate, which will then increase

the baseband of the input signals to be converted. The

digital gain (which is enabled at 32x and 64x gains) has

no influence on the achievable bandwidth.

A typical dependency of the bandwidth depending on

the gain for each BOOST setting combination is shown

from Figure 2-35 to Figure 2-38. Typically, a larger gain

setting requires a higher BOOST setting in order to

achieve the same bandwidth performance.

Figure 2-43 shows the behavior of the achievable band-

width at BOOST[1:0] = 1x with AVDD corner cases. Since

the BOOST settings vary, the internal slew rate of the

modulator components, using a lower VREF value, will

improve the bandwidth if low BOOST settings are used

and show a bandwidth behavior that is too limited.

5.5

Digital Decimation Filter

The decimation filter decimates the output bit stream of

the modulator to produce 16-bit ADC output data. The

decimation filter present in the device is a cascade of two

filters: a third-order sinc filter with a decimation ratio of

OSR3 (third order moving an average of 3 x OSR3

values), followed by a first-order sinc filter with a decima-

tion ratio of OSR1, moving an average of OSR values

(third order moving average of 3 x OSR3 values).

Figure 5-4 represents the decimation filter architecture.

FIGURE 5-4:

Decimation Filter Block

Diagram.

Equation 5-3 is the transfer function of the decimation

filter:

EQUATION 5-3:

FILTER TRANSFER

FUNCTION

TABLE 5-5:

BOOST SETTINGS

DESCRIPTION

BOOST[1:0]

Bias Current

x0.5

x0.66

x1 (default)

AMCLK

tDOMDAT

MDAT

(code = +2)

MDAT

(code = +1)

MDAT

(code = 0)

MDAT

(code = -1)

MDAT

(code = -2)

COMP[3]

C OMP[2]

COMP[1]

C OMP[0]

tDOMDAT tDOMDAT tDOMDAT tDOMDAT

Modulator

Output

(Thermometer

Coding)

SINC

Decimation

Filter

Output

OSR3

OSR1

ADC

Resolution

Decimation Filter

OSR1 = 1



-OSR3

–





OSR3 1z 1

–



3

--------------------------------------------

-OSR1 OSR3



–





OSR

OSR3

–







------------------------------------------------------



Where:

fj

DMCLK

----------------------





exp

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