LM3495 datasheet(22/26 Pages) NSC

22 / 26 page

Layout Considerations (Continued)

cap to the pin itself. This trace should also be used to

connect to the top of the feedback resistors. Keep this trace

away from the switch node and from the output inductor.

SEPARATE PGND AND SGND

Good layout techniques include a dedicated ground plane,

usually on an internal layer. Signal level components like the

compensation and feedback resistors should be connected

to a section of this internal plane, SGND. The SGND section

of the plane should be connected to the power ground at

only one point. The best place to connect the SGND and

PGND is right at the SGND pin.

MINIMIZE THE SWITCH NODE

The plane that connects the power FETs and output inductor

together radiates more EMI as it gets larger. Use just enough

copper to give low impedance to the switching currents.

LOW IMPEDANCE POWER PATH

The power path includes the input capacitors, power FETs,

output inductor, and output capacitors. Keep these compo-

nents on the same side of the PCB and connect them with

thick traces or copper planes (shapes) on the same layer.

Vias add resistance and inductance to the power path, and

have high impedance connections to internal planes than to

the top of bottom layers of a PCB. If heavy switching currents

must be routed through vias and/or internal planes, use

multiple vias in parallel to reduce their resistance and induc-

tance. The power components should be kept close to-

gether. The longer the paths that connect them, the more

they act as antennas, radiating unwanted EMI.

LM3495 Datasheet(PDF) 22 Page - National Semiconductor (TI)