73K221AL datasheet(2/26 Pages) TDK

2 / 26 page

73K222BL

V.22, V.21, Bell 212A, Bell 103

Single-Chip Modem with Integrated Hybrid

DESCRIPTION (continued)

The 73K222BL is designed to appear to the systems

designer as a microprocessor peripheral, and will

easily

interface

with

popular

one-chip

microprocessors (80C51 typical) for control of

modem functions through its 8-bit multiplexed

address/data bus. An ALE control line simplifies

address

demultiplexing.

Data

communications

occurs through a separate serial port only.

The 73K222BL is ideal for use in either free standing

or integral system modem products where full-

duplex 1200 bit/s data communications over the 2-

wire switched telephone network is desired. Its high

functionality, low power consumption and efficient

packaging

simplify

design

requirements

and

increase system reliability. A complete modem

requires only the addition of the phone line interface,

control

microprocessor,

and

RS-232

level

converter for a typical system.

The 73K222BL is part of TDK Semiconductor’s

K-Series family of single-chip modem products.

These devices allow systems to be configured for

higher speeds and Bell or CCITT operation with only

a single component change.

FUNCTIONAL DESCRIPTION

HYBRID AND RELAY DRIVER

To make designs more cost effective and space

efficient, the 73K222BL includes the 2-wire to 4-wire

hybrid with sufficient drive to interface directly to the

telecom coupling transformers. In addition, an off

hook relay driver with 40 mA drive capability is also

included to allow use of commonly available

mechanical telecom relays.

ASYNCHRONOUS MODE

Data transmission for the DPSK mode requires that

data ultimately be transmitted in a synchronous

fashion. The 73K222BL includes ASYNC/SYNC and

SYNC/ASYNC converters which delete or insert stop

bits in order to transmit data within a ±0.01% rate. In

asynchronous mode the serial data comes from the

TXD pin into the ASYNC/SYNC converter. The

ASYNC/SYNC converter accepts the data provided

on the TXD pin which normally must be 1200 or 600

bit/s +1.0%, -2.5%. The converter will then insert or

delete stop bits in order to output a signal which is

1200 or 600 bit/s ± 0.01% (± 0.01% is required

synchronous data rate accuracy).

The serial data stream from the ASYNC/SYNC

converter is passed through the data scrambler and

onto the analog modulator. The data scrambler can

bypassed

under

processor

control

when

unscrambled data must be transmitted. The

ASYNC/SYNC converter and the data scrambler are

bypassed in all FSK modes. If serial input data

contains a break signal through one character

(including start and stop bits) the break will be

extended to at least 2

• N + 3 bits long (where N is

the number of transmitted bits/character).

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