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73K221AL Datasheet(PDF) 10 Page - TDK Electronics

Part # 73K221AL
Description  V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid
PDF  26 Pages
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Manufacturer  TDK [TDK Electronics]
Direct Link  http://www.tdk.com
Logo TDK - TDK Electronics

73K221AL Datasheet(HTML) 10 Page - TDK Electronics

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73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid
10
CONTROL REGISTER 0 (continued)
D7
D6
D5
D4
D3
D2
D1
D0
CR0
000
MODUL.
OPTION
0
TRANSMIT
MODE 3
TRANSMIT
MODE 2
TRANSMIT
MODE 1
TRANSMIT
MODE 0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
BIT NO.
NAME
CONDITION
DESCRIPTION
D7
D5
D4
Selects:
0
0
X
DPSK mode at 1200 bit/s.
1
0
X
DPSK mode at 600 bit/s.
0
1
1
FSK Bell 103 mode.
1
1
1
FSK CCITT V.21 mode.
D7
Modulation
Option
X = Don’t care
CONTROL REGISTER 1
D7
D6
D5
D4
D3
D2
D1
D0
CR1
001
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
BYPASS
SCRAMB
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
BIT NO.
NAME
CONDITION
DESCRIPTION
D1
D0
00
Selects normal operating mode
0
1
Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low.
10
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
D1, D0
Test Mode
11
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.
0
Selects normal operation.
D2
Reset
1
Resets
modem
to
power-down
state.
All
control register bits (CR0, CR1, TONE) are reset to
zero. The output of the CLK pin will be set to the
crystal frequency. This bit clears itself.
0
Selects 11.0592 MHz crystal echo output at CLK pin.
D3
CLK Control
(Clock Control)
1
Selects 16 times the data rate, output at CLK pin in
DPSK modes only.



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