AD9779 datasheet(13/34 Pages) AD

13 / 34 page

Preliminary Technical Data

AD9779

Rev. PrD | Page 13 of 34

this pin. However, this pin can be used as a bidirectional data line.

The configuration of this pin is controlled by Bit 7 of register

address 00h. The default is Logic 0, which configures the SDIO pin

as unidirectional.

SDO—Serial Data Out

. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the

case where the AD9779 operates in a single bidirectional I/O mode,

this pin does not output data and is set to a high impedance stat

MSB/LSB Transfers

The AD9779 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by register bit LSBFIRST (REG00, bit 6).

The default is MSB first (LSBFIRST = 0).

When LSBFIRST = 0 (MSB first) the instruction and data bytes

must be written from most significant bit to least significant bit.

Multibyte data transfers in MSB first format start with an

instruction byte that includes the register address of the most

significant data byte. Subsequent data bytes should follow in order

from high address to low address. In MSB first mode, the serial

port internal byte address generator decrements for each data byte

of the multibyte communication cycle.

When LSBFIRST = 1 (LSB first) the instruction and data bytes

must be written from least significant bit to most significant bit.

Multibyte data transfers in LSB first format start with an

instruction byte that includes the register address of the least

significant data byte followed by multiple data bytes. The serial port

internal byte address generator increments for each byte of the

multibyte communication cycle.

The AD9779 serial port controller data address will decrement

from the data address written toward 0x00 for multibyte I/O

operations if the MSB first mode is active. The serial port controller

address will increment from the data address written toward 0x1F

for multibyte I/O operations if the LSB first mode is active.

Notes on Serial Port Operation

The AD9779 serial port configuration is controlled by REG00, bits

6 and 7 . It is important to note that the configuration changes

immediately upon writing to the last bit of the register. For

multibyte transfers, writing to this register may occur during the

middle of communication cycle. Care must be taken to compensate

for this new configuration for the remaining bytes of the current

communication cycle.

The same considerations apply to setting the software reset, RESET

(REG00, bit 5). All registers are set to their default values EXCEPT

REG00 and REG04 which remain unchanged.

Use of only single byte transfers when changing serial port

configurations or initiating a software reset is recommended to

prevent unexpected device behavior.

R/W N0

A0 A1

D7 D6N D5N

D00

D10

D20

D30

D7 D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 25. Serial Register Interface Timing MSB First

A3 A4

N0 R/W D00 D10 D20

D7N

D6N

D5N

D4N

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 26. Serial Register Interface Timing LSB First

INSTRUCTION BIT 6

INSTRUCTION BIT 7

CSB

SCLK

SDIO

tDS

tDH

tPWH

tPWL

tSCLK

Figure 27. Timing Diagram for SPI Register Write

DATA BIT n–1

DATA BIT n

CSB

SCLK

SDIO

SDO

tDV

Figure 28. Timing Diagram for SPI Register Read

AD9779 Datasheet(PDF) 13 Page - Analog Devices

AD9779 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL