AD7993 datasheet(22/32 Pages) AD

22 / 32 page

AD7993/AD7994

Rev. 0 | Page 22 of 32

CYCLE TIMER REGISTER

The cycle timer register is an 8-bit read/write register that stores

the conversion interval value for the automatic cycle interval

mode of the AD7993/AD7994 (see the Modes of Operation

section). D5 to D3 of the cycle timer register are unused and

should contain 0s at all times. On power-up, the cycle timer

of the AD7993/AD7994. To enable automatic cycle mode, the

user must write to the cycle timer register, selecting the required

conversion interval. Table 24 shows the structure of the cycle

timer register while Table 25 shows how the bits in this register

are decoded to provide various automatic sampling intervals.

Table 24. Cycle Timer Register and Default Power-Up Settings

Sample

Delay

Bit Trial

Delay

Cyc

Bit2

Cyc

Bit1

Cyc

Bit0

Table 25. Cycle Timer Intervals

Typical Conversion Interval

(TCONVERT = conversion time of the ADC)

Mode not selected

TCONVERT × 32

TCONVERT × 64

TCONVERT × 128

TCONVERT × 256

TCONVERT × 512

TCONVERT × 1024

TCONVERT × 2048

SAMPLE DELAY AND BIT TRIAL DELAY

It is recommended that no I2C bus activity occur when a

conversion is taking place. However, if this is not possible, for

example when operating in Mode 2 or Mode 3, then in order to

maintain the performance of the ADC, Bits D7 and D6 in the

cycle timer register are used to delay critical sample intervals

and bit trials from occurring while there is activity on the I2C

bus. This results in a quiet period for each bit decision. In

certain cases where there is excessive activity on the interface

lines, this may have the effect of increasing the overall

conversion time. However, if bit trial delays extend longer than

1 µs, the conversion terminates.

When Bits D7 and D6 are both 0, the bit trial and sample

interval delaying mechanism is implemented. The default

setting of D7 and D6 is 0. To turn off both delay mechanisms,

set D7 and D6 to 1.

Table 26. Cycle Timer Register and Defaults at Power-Up

Sample

Delay

Bit Trial

Delay

Cyc

Bit 2

Cyc

Bit 1

Cyc

Bit 0

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