AD8230

Rev. 0 | Page 10 of 16

THEORY OF OPERATION

Auto-zeroing is a dynamic offset and drift cancellation tech-

nique that reduces input referred voltage offset to the µV level

and voltage offset drift to the nV/°C level. A further advantage

of dynamic offset cancellation is the reduction of low frequency

noise, in particular the 1/f component.

The AD8230 is an instrumentation amplifier that uses an

auto-zeroing topology and combines it with high common-

mode signal rejection. The internal signal path consists of an

active differential sample-and-hold stage (preamp) followed by

a differential amplifier (gain amp). Both amplifiers implement

auto-zeroing to minimize offset and drift. A fully differential

topology increases the immunity of the signals to parasitic noise

and temperature effects. Amplifier gain is set by two external

resistors for convenient TC matching.

The signal sampling rate is controlled by an on-chip, 6 kHz

oscillator and logic to derive the required nonoverlapping

clock phases. For simplification of the functional description,

two sequential clock phases, A and B, are used to distinguish

the order of internal operation, as depicted in Figure 27 and

Figure 28, respectively.

–

–

+

+

PREAMP

GAIN AMP

Figure 27. Phase A of the Sampling Phase

During Phase A, the sampling capacitors are connected to the

capacitors only retain the difference voltage, the common-mode

voltage is rejected. During this period, the gain amplifier is not

connected to the preamplifier so its output remains at the level

shown in Figure 27.

–

–

+

+

PREAMP

GAIN AMP

Figure 28. Phase B of the Sampling Phase

In Phase B, the differential signal is transferred to the hold

the preamplifier is held at a common-mode voltage determined

able to condition the difference signal and set the output voltage

level. The gain amplifier conditions the updated signal stored on

SETTING THE GAIN

Two external resistors set the gain of the AD8230. The gain is

expressed in the following function:

)

2(1

G

F

R

R

Gain

+

=

2

6

1

7

5

8

4

3

AD8230

0.1

µF

0.1

µF

10

µF

10

µF

Figure 29. Gain Setting

Table 4. Gains Using Standard 1% Resistors

Gain

Actual Gain

2

0 Ω (short)

None

2

10

8.06 kΩ

2 kΩ

10

50

12.1 kΩ

499 Ω

50.5

100

9.76 kΩ

200 Ω

99.6

200

10 kΩ

100 Ω

202

500

49.9 kΩ

200 Ω

501

1000

100 kΩ

200 Ω

1002

Figure 29 and Table 4 provide an example of some gain settings.

As Table 4 shows, the AD8230 accepts a wide range of resistor

values. Since the instrumentation amplifier has finite driving

capability, make sure that the output load in parallel with the

sum of the gain setting resistors is greater than 2 kΩ.

Offset voltage drift at high temperature can be minimized by

of the gain setting resistor on offset voltage drift is shown in

Figure 30. In addition, experience has shown that wire-wound

resistors in the gain feedback loop may degrade the offset

voltage performance.