UTC571 datasheet(6/14 Pages) UTC

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UTC571

LINEAR INTEGRATED CIRCUIT

YOUW ANG ELECTRONICS CO.LTD

BASIC CIRCUIT HOOK-UP AND OPERATION

20K

10K

20K

30K

GIN

RECTIN

3.14

2.15

1.16

CRECT

VREE

1.8V

VCC PIN 13

GND PIN 4

OUTPUT

7.10

5.12

6.11

8.9

THD TRIM

INVIN

Figure 2. Chip Block Diagram

Figure 2 shows the block diagram of one half of the chip, (there are two identical channels on the IC). The full-

wave averaging rectifier provides a gain control current, IG , for the variable gain

(∆G) cell. The output of the DG

cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish

circuit gain and set the output DC bias.

The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at

some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.8V

reference denoted VREF . The non-inverting input of the op amp is tied to VREF , and the

summing nodes of the

rectifier and

∆G cell (located at the right of R1 and R2) have the same potential. The THD trim pin is also the VREF

potential.

VREF

VOUT

VIN

CIN1

CIN2

CRECT

NOTE: GAIN= 2R3VIN (avg)

R1R2IB

IB=140

Figure 3. Basic Expander

Figure 3 shows how the circuit is hooked up to realize an expandor. The input signal, VIN is applied to the inputs

of both the rectifier and the

∆G cell. When the input signal drops by 6dB, the gain control current will drop by a

factor of 2, and so the gain will drop 6dB. The output level at VOUT will thus drop 12dB, giving us the desired 2 to 1

expansion.

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