PCI Express™ Jitter Attenuator

874005 DATA SHEET

4

REVISION B 7/20/15

TABLE 4D. LVDS DC CHARACTERISTICS, V

DD = VDDA = VDDO = 3.3V±5%, T

A

= 0°C TO 70°C

TABLE 5. AC CHARACTERISTICS, V

DD = VDDA = VDDO = 3.3V±5%, T

A

= 0°C TO 70°C

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V

DD = VDDA = VDDO = 3.3V±5%, T

A

= 0°C TO 70°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

I

IH

Input High Current

CLK

V

DD = VIN = 3.465V

150

µA

nCLK

V

DD = VIN = 3.465V

5

µA

I

IL

Input Low Current

CLK

V

DD = VIN = 3.465V

-5

µA

nCLK

V

DD = VIN = 3.465V

-150

µA

V

PP

Peak-to-Peak Input Voltage

0.15

1.3

V

V

CMR

Common Mode Input Voltage; NOTE 1, 2

GND + 0.5

V

DD - 0.85

V

NOTE 1: Common mode voltage is defined as V

IH.

NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V

DD + 0.3V.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

OD

Differential Output Voltage

275

375

485

mV

Δ V

OD

V

OD Magnitude Change

50

mV

V

OS

Offset Voltage

1.2

1.35

1.5

V

Δ V

OS

V

OS Magnitude Change

50

mV

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Output Frequency

98

160

MHz

tjit(cc)

Cycle-to-Cycle Jitter, NOTE 1

15

30

ps

tsk(o)

Output Skew; NOTE 2, 3

90

ps

t

R / tF

Output Rise/Fall Time

20% to 80%

300

550

ps

odc

Output Duty Cycle

48

52

%

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established

when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet

specifications after thermal equilibrium has been reached under these conditons.

NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V

DDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.