PCI Express™ Jitter Attenuator

874005

DATA SHEET

874005 REVISION B 7/20/15

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©2015 Integrated Device Technology, Inc.

GENERAL DESCRIPTION

The 874005 is a high performance Differential-to-LVDS Jitter

Attenuator designed for use in PCI Express systems. In some

PCI Express systems, such as those found in desktop PCs, the

PCI Express clocks are generated from a low bandwidth, high

phase noise PLL frequency synthesizer. In these systems, a jitter

attenuator may be required to attenuate high frequency random

and deterministic jitter components from the PLL synthesizer

and from the system board. The 874005 has 3 PLL bandwidth

modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will

provide maximum jitter attenuation, but with higher PLL tracking

skew and spread spectrum modulation from the motherboard

synthesizer may be attenuated. The 400kHz provides an

intermediate bandwidth that can easily track triangular spread

profiles, while providing good jitter attenuation. The 800kHz

bandwidth provides the best tracking skew and will pass most

spread profiles, but the jitter attenuation will not be as good

as the lower bandwidth modes. Because some 2.5Gb serdes

have x20 multipliers while others have than x25 multipliers, the

874005 can be set for 1:1 mode or 5/4 multiplication mode (i.e.

100MHz input/125MHz output) using the F_SEL pins.

The 874005 uses IDT’s 3rd Generation FemtoClock®

PLL technology to achive the lowest possible phase noise.

The device is packaged in a 24 Lead TSSOP package, making

it ideal for use in space constrained applications such as PCI

Express add-in cards.

FEATURES

• Five differential LVDS output pairs

• One differential clock input

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency range: 98MHz - 160MHz

• Input frequency range: 98MHz - 128MHz

• VCO range: 490MHz - 640MHz

• Cycle-to-cycle jitter: 30ps (maximum)

• 3.3V operating supply

• 3 bandwidth modes allow the system designer to make

jitter attenuation/tracking skew design trade-offs

• 0°C to 70°C ambient operating temperature

• Available in lead-free RoHS compliant package

BLOCK DIAGRAM

BW_SEL

0 = PLL Bandwidth: ~200kHz

Float = PLL Bandwidth: ~400kHz (Default)

1 = PLL Bandwidth: ~800kHz

PLL BANDWIDTH

PIN ASSIGNMENT

874005

24-Lead TSSOP

4.40mm x 7.8mm x 0.92mm

package body

G Package

Top View

nQB2

nQA1

QA1

VDDO

QA0

nQA0

MR

BW_SEL

VDDA

F_SELA

VDD

OEA

1

2

3

4

5

6

7

8

9

10

11

12

QB2

VDDO

QB1

nQB1

QB0

nQB0

F_SELB

OEB

GND

GND

nCLK

CLK

24

23

22

21

20

19

18

17

16

15

14

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