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AT25QL641 Datasheet(PDF) 31 Page - Renesas Technology Corp

Part # AT25QL641
Description  SPI Serial Flash Memory with Dual I/O, Quad I/O, QPI Support
PDF  80 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25QL641 Datasheet(HTML) 31 Page - Renesas Technology Corp

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DS-AT25QL641-130 Rev. G
Page 31
Sep 14, 2022
© 2022 Renesas Electronics
AT25QL641 Datasheet
8.12 Fast Read Quad Output (6Bh)
By using four pins (I/O0, I/O1, I/O2, and I/O3), the Fast Read Quad Output command allows data to be
transferred from the AT25QL641 at four times the rate of standard SPI devices. A Quad enable of Status Register-
2 must be executed before the device accepts the Fast Read Quad Output command (Status register bit QE must
equal 1).
The Fast Read Quad Output command can operate at the highest possible frequency of FR (see Table 26, AC
Electrical Characteristics). This is accomplished by adding eight dummy clocks after the 24-bit address as
shown in Figure 19. The dummy clocks allow the internal circuits additional time for setting up the initial address.
During the dummy clocks, the data value on the SO pin is a don’t care. However, the I/O0 pin should be high-
impedance prior to the falling edge of the first data out clock.
Figure 19. Fast Read Quad Output Command (SPI Mode)
39 40
41
42
43
44
45
31 32 33
34
35
36
37
38
46
47
35
246
7
28
30
10
29
31
9
8
23
22
21
3
2
1
0
0
0
1
Mode 3
Mode 0
High-Impedance
High-Impedance
SCK
CS
SCK
CS
Command (6Bh)
24-Bit Address
MSB
Dummy Clocks
Byte 1
Byte 2
Byte 3
Byte 4
7
6
3
4
2
04
6
7
High-Impedance
5
High-Impedance
51
7
6
3
4
2
0
51
7
6
3
4
2
0
51
7
6
3
4
2
0
51
High-Impedance
High-Impedance
IO
0 switches from
Input to Output
IO
IO
IO
IO
IO
IO
IO
IO



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