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AT25QL641 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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AT25QL641 Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 80 page ![]() DS-AT25QL641-130 Rev. G Page 10 Sep 14, 2022 © 2022 Renesas Electronics AT25QL641 Datasheet 3. Block Diagram Figure 3 shows a block diagram of the AT25QL641 serial Flash. Figure 3. AT25QL641 Block Diagram Flash Memory Array Y-Gating CS SCK Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands. * Hardware-controlled RESET available ONLY on packages with greater than eight pins. SO (I/O1) SI (I/O0) Y-Decoder X-Decoder I/O Buffers and Latches Control and Protection Logic SRAM Data Buffer WP (I/O2) Interface Control And Logic HOLD (I/O3) RESET* |
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