AT25QL641 datasheet(69/80 Pages) RENESAS

69 / 80 page

DS-AT25QL641-130 Rev. G

Page 69

Sep 14, 2022

AT25QL641 Datasheet

8.39 Write Security Register (2Fh)

The Write Security Register command is for change the state of the bits in the Security Register. Unlike the

Write Status Register command, the Write Enable command is not required before executing the Write Security

kbit Secured OTP area. Once the LDSO bit is set to 1, the Secured OTP area cannot be updated any more.

The CS must go high exactly at the boundary; otherwise, the command is not executed.

Figure 64. Write Security Register Command for SPI Mode (left) and QPI Mode (right)

8.40 4-kbit Secured OTP

The AT25QL641 provides a 4-kbit one-time-program area for setting a unique serial number which can be set

by either the factory or the customer. Security register bit 0 indicates whether the chip is locked by factory or not.

The 4-kbit OTP space is accessed using the B1h command as described above. After the OTP value has been

programmed, the C1h command is used to exit from the secured OTP space.

The secure OTP space is divided into a 128-bit electronic serial number, and 3968 bits is user-defined data as

shown in Table 19.

Note. Once the OTP space is locked down, either by the factory or the customer, it cannot be changed any

more. While in 4-kbit secured OTP mode, array access is not allowed to write.

Table 19. Secure OTP Address Space

Address Range

Size

Standard

Customer Lock

000000 ~ 00000F

128-bit

ESN

(Electrical Serial Number)

Determined by customer

000010 ~ 0001FF

3968-bit

N/A

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