AT25QL641 datasheet(36/80 Pages) RENESAS

36 / 80 page

DS-AT25QL641-130 Rev. G

Page 36

Sep 14, 2022

AT25QL641 Datasheet

8.15 Page Program (02h)

The Page Program command is for programming the memory to be 0. A Write Enable command must be issued

before the device accept the Page Program Command (Status Register bit WEL= 1). After the Write Enable

(WREN) command has been decoded, the device sets the Write Enable Latch (WEL). The command is entered

by driving the CS pin low and then sending the command code 02h followed by a 24-bits address (A23-A0) and

at least one data byte on the SI pin. The CS pin must be driven low for the entire time of the command while data

is being sent to the device. (See Figure 25 and Figure 26.)

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should

be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length,

the addressing wraps around to the beginning of the page. In some cases, less than 256 bytes (a partial page)

can be programmed without having any effect on other bytes within the same page. One condition to perform a

partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256

bytes are sent to the device the addressing wraps around to the beginning of the page and overwrites previously

sent data.

The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done, the Page

Program command is not executed. After CS is driven high, the self-timed Page Program command

commences for a time duration of tPP (see Table 26, AC Electrical Characteristics). While the page program

operation is in progress, the Read Status Register command may still be accessed for checking the status of the

BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and

the device is ready to accept other commands again. When the BUSY bit is asserted, the Write Enable Latch

(WEL) bit in the Status Register is cleared to 0.

Figure 25. Page Program Command (SPI Mode)

32 33

38 39

SCK

Command (02h)

24-Bit Address

Data Byte 1

321

076

543

210

123

89 10

Mode 3

Mode 0

44 45

50 51 52 53

SCK

Data Byte 2

Data Byte 3

Data Byte 256

543

210

543

210

543

210

Mode 3

Mode 0

MSB

AT25QL641 Datasheet(PDF) 36 Page - Renesas Technology Corp

AT25QL641 Datasheet(HTML) 36 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL