COMMERCIALTEMPERATURERANGE

IDTCV141

1-TO-8DIFFERENTIALCLOCKBUFFER

7

DIF AC TIMING CHARACTERISTICS

PLL Bandwidth and Peaking

Symbol

Parameter

Min

Typ

Max

Units

TPROP,PLL

SRC_IN to DIF Propagation Delay, PLL Mode(1)

-250

—

250

ps

TPROP,BYPASS

SRC_IN to DIF Propagation Delay, Bypass Mode(1)

2.5

—

4.5

ns

TSKEW

DIF_[7:0] Pin to Pin Skew(1)

—

—

250

ps

PLLbandwidth

HIGH_BW#=0 (high bandwidth)(1)

2

3

4

MHz

PLLbandwidth

HIGH_BW#=1 (low bandwidth)(1)

0.7

1

1.4

MHz

PLL Peaking

PLL Peaking(1,2)

—1

3

dB

TCCJITTER

Cycle to Cycle Jitter(1)

——

50

pS

Duty cycle

PLL Mode(1)

45

—

55

%

Duty cycle

Bypass (assume input is 50%)(1)

40

—

60

%

OUTPUTCONTROL

Symbol

Parameter

Min

Typ

Max

Units

TDRIVE_PWRDWN

CLK driven from PD De_Assertion

—

—

300

μs

TACTIVE_PWRDWN

CLK Toggling from PD De_Assertion

—

—

1

ms

TACTIVE_OE

CLK toggling from OE_[7:0] Assertion

2

—

6

Clock Periods

TINACTIVE_OE

CLK Tri-stated from OE_[7:0] De_Assertion

2

—

6

Clock Periods

PWRDWN (OE_INV = 0)

The PWRDWN signal is a de-bounced signal in that its state must remain unchanged

during two consecutive rising edges of DIF# to be recognized as a valid assertion or

de-assertion.

PWRDWN

DIF

DIF#

1

Normal

Normal

0

Iref*2 or Float

Float

SRC_STOP (OE_INV = 0)

The SRC_STOP signal is a de-bounced signal in that its state must remain unchanged

during two consecutive rising edges of DIF# to be recognized as a valid assertion or de-

assertion.

SRC_STOP

DIF

DIF#

1

Normal

Normal

0

Iref*6 or Float

Float

PWRDWN (OE_INV = 1)

PWRDWN

DIF

DIF#

1

Iref*2 or Float

Float

0

Normal

Normal

SRC_STOP (OE_INV = 1)

SRC_STOP

DIF

DIF#

1

Iref*6 or Float

Float

0

Normal

Normal

NOTES:

1.

This parameter is guaranteed by design, but not 100% production tested.

2.

Measured at 3dB downpoint.