COMMERCIALTEMPERATURERANGE

IDTCV141

1-TO-8DIFFERENTIALCLOCKBUFFER

1

OCTOBER 2005

IDTCV141

COMMERCIAL TEMPERATURE RANGE

1-TO-8 DIFFERENTIAL

CLOCK BUFFER

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

© 2005 Integrated Device Technology, Inc.

DSC 6738/19

FEATURES:

• Compliant with Intel DB800 spec

• Eight differential clock pairs at 0.7V

• 50ps skew

• 50ps cycle-to-cycle jitter

• Programmable Bandwidth

• PLL bypass configurable

• Divide by 2 programmable

• Available in SSOP and TSSOP packages

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The CV141 differential buffer is compliant with Intel DB800 specifications. It

is intended to distribute the SRC (serial reference clock) as a companion chip

to the main clock of the CK409, CK410/CK410M, CK410B, etc. PLL is off in

bypass mode and has no clock detect.

DIV

PLL

Output

Buffer

DIF_0

DIF_0#

DIF_1

DIF_1#

DIF_2

DIF_2#

DIF_3

DIF_3#

DIF_4

DIF_4#

DIF_5

DIF_5#

DIF_6

DIF_6#

DIF_7

DIF_7#

SCL

SDA

SRC_DIV2#

SRC_IN#

SRC_IN

Output

Control

HIGH_BW#

PLL/BYPASS#

OE[7:0]

SRC_STOP

PWRDWN

SM Bus

Controller

LOCK

OE_INV

(1)

(1)

(1)

NOTE:

1. See OE_INV table for active HIGH or active LOW.