CV145 datasheet(9/14 Pages) RENESAS

9 / 14 page

COMMERCIALTEMPERATURERANGE

IDTCV145

1-TO-19DIFFERENTIALCLOCKBUFFER

OUTPUT RELATIONAL TIMING PARAMETERS

PLL BANDWIDTH AND PEAKING

DC OPERATING CHARACTERISTICS

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: VDD/VDDA = 3.3V ± 5%

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VDDA

3.3 V Core Supply Voltage

3.3 V ±5%

3.135

3.465

VDD

3.3 V I/O Supply Voltage

3.3 V ±5%

3.135

3.465

IDD

3.3 V Supply Current

3.3 V ±5%, 0 to 70C

450

600

IDDPD

3.3 V Power Down Supply Current

3.3 V ±5%, 0 to 70C

VIH

3.3 V Input High Voltage

Vdd

2.0

Vdd+0.3

VIL

3.3 V Input Low Voltage

Vss-0.3

0.8

IIL

Input Leakage Current

0 < Vin < Vdd

-5

µA

Cin

Input Pin Capacitance

1.5

Cout

Output Pin Capacitance

Lpin

Pin Inductance

Ambient Temperature

No Airflow

°C

Group

Parameter

Min.

Typ.

Max.

CLK_IN, DIF [x:0]

Input to Output Skew in PLL mode (1:1 only)

-500ps

+500ps

CLK_IN, DIF [x:0]

Input to Output Skew in non PLL mode (1:1 only)

2.5ns

4.5ns

DIF

DIFF[x:0] Pin-to-Pin Skew (output within same group)

0ps

115

125ps

DIF

DIFF[x:0] Pin-to-Pin Skew (across all outputs)

0ps

115

150ps

DIF

Accumulated Differential Phase Jitter

-100ps

+100ps

Group

Parameter

Min.

Typ.

Max.

Unit

DIF

PLL Peaking (HIGH_BW# = 0)

2.5

DIF

PLL Peaking (HIGH_BW# = 1)

DIF

PLL Bandwidth (HIGH_BW# = 0)

3.8

MHz

DIF

PLL Bandwidth (HIGH_BW# = 1)

0.7

0.9

1.4

MHz

Output phase jitter impact

(PCIe: including BW 1.5-22Mhz)

108

Output phase jitter impact

(FBD/CSI: including BW 11-33Mhz)

-3

Rms

DIF

CV145 Datasheet(PDF) 9 Page - Renesas Technology Corp

CV145 Datasheet(HTML) 9 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet Download

Link URL