87LPC769 datasheet(14/61 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

87LPC769

Low power, low price, low pin count (20 pin)

microcontroller with 4 kB OTP 8-bit A/D, and DAC

2001 Jan 11

RC clock frequency of 4.5 MHz (6 MHz - 25%). Minimum times for

RCCLK = 1 use an RC clock frequency of 7.5 MHz (6 MHz + 25%).

Nominal time assume an ideal RC clock frequency of 6 MHz and an

average of 3.5 machine cycles at the CPU clock rate.

Table 1. Example A/D Conversion Times

CPU Clock Rate

RCCLK = 0

RCCLK = 1

CPU Clock Rate

RCCLK = 0

minimum

nominal

maximum

32 kHz

563.4

µs

659

µs

757

µs

1 MHz

186

µs

32.4

µs

39.3

µs

48.9

µs

4 MHz

46.5

µs

18.9

µs

23.6

µs

30.1

µs

Note: Do not clock ADC from the RC oscillator when MCU clock is greater than 4 MHz.

AD0 (P0.3)

AD1 (P0.4)

VREF+ = VDD

AADR1

AD2 (P0.5)

AD3 (P0.6)

VREF- = VSS

ADCON

A/D Converter

AADR0

DAC0

(A/D result)

SU01356

Figure 3. A/D Converter Connections

The A/D in Power Down and Idle Modes

While using the CPU clock as the A/D clock source, the Idle mode

may be used to conserve power and/or to minimize system noise

during the conversion. CPU operation will resume and Idle mode

terminate automatically when a conversion is complete if the A/D

interrupt is active. In Idle mode, noise from the CPU itself is

eliminated, but noise from the oscillator and any other on-chip

peripherals that are running will remain.

The CPU may be put into Power Down mode when the A/D is

clocked by the on-chip RC oscillator (RCCLK=1). This mode gives

the best possible A/D accuracy by eliminating most on-chip noise

sources.

If the Power Down mode is entered while the A/D is running from the

CPU clock (RCCLK=0), the A/D will abort operation and will not

wake up the CPU. The contents of DAC0 will be invalid when

operation does resume.

When an A/D conversion is started, Power Down or Idle mode must

be activated within two machine cycles in order to have the most

accurate A/D result. These two machine cycles are counted at the

CPU clock rate. When using the A/D with either Power Down or Idle

mode, care must be taken to insure that the CPU is not restarted by

another interrupt until the A/D conversion is complete. The possible

causes of wakeup are different in Power Down and Idle modes.

A/D accuracy is also affected by noise generated elsewhere in the

application, power supply noise, and power supply regulation. Since

the 87LPC769 power pins are also used as the A/D reference and

supply, the power supply has a very direct affect on the accuracy of

A/D readings. Using the A/D without Power Down mode while the

clock is divided through the use of CLKR or DIVM has an adverse

effect on A/D accuracy.

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