LM3743 datasheet(12/23 Pages) NSC

12 / 23 page

Application Information

THEORY OF OPERATION

The LM3743 is a voltage mode PWM buck controller featur-

ing synchronous rectification at 300 kHz or 1 MHz. In steady

state operation the LM3743 is always synchronous even at

no load, thus simplifying the compensation design. The

LM3743 ensures a smooth and controlled start-up to support

pre-biased outputs. Two levels of current limit protection

enhance the robustness of the power supply and requires no

current sense resistor in the power path. The primary level of

protection is the low side current limit and is achieved by

sensing the voltage V

DS across the low side MOSFET. The

second level of protection is the high side current limit, which

protects power components from extremely high currents,

caused by switch node short to ground.

NORMAL OPERATION

While in normal operation, the LM3743 IC controls the output

voltage by controlling the duty cycle of the power FETs. The

DC level of the output voltage is determined by a pair of

feedback resistors using the following equation:

(Designators refer to the Typical Application Circuit in the

front page)

For synchronous buck regulators, the duty ratio D is approxi-

mately equal to:

START UP

The LM3743 IC begins to operate when the COMP/EN pin is

released from a clamped condition and the voltage at the

CC pin has exceeded 2.84V. Once these two conditions

have been met the internal 10µA current source begins to

charge the soft-start capacitor connected at the SS/TRACK

pin. During soft-start the voltage on the soft-start capacitor is

connected internally to the non-inverting input of the error

amplifier. The soft-start period lasts until the voltage on the

soft-start capacitor exceeds the LM3743 reference voltage

of 0.8V. At this point the reference voltage takes over at the

non-inverting error amplifier input. The capacitance deter-

mines the length of the soft-start period, and can be approxi-

mated by:

C4=(t

SS x 10 µA) / 0.8V

Where t

SS is the desired soft-start time. In the event of either

CC falling below UVLO or COMP/EN pin being pulled below

0.45V, the soft-start pin will discharge C4 to allow the output

voltage to recover smoothly.

START UP WITH PRE-BIAS

A pre-bias output is a condition in which current from another

source has charged up the output capacitor of the switching

regulator before it has been turned on. The LM3743 features

a proprietary glitch free monotonic pre-bias start-up method

designed to ramp the output voltage from a pre-biased rail to

the target nominal output voltage. The IC limits the on time of

the low-side FET to 150 ns (typ) during soft-start, while

allowing the high-side FET to adjust it’s time according to

soft-start voltage, V

OUT, and the internal voltage ramp. Any

further commutation of the load current is carried by the body

diode of the low-side FET or an external Schottky diode, if

used. The low side current limit is active during soft-start

while allowing the asynchronous switching. When soft-start

is completed, the on-time of the low-side FET is allowed to

increase in a controlled fashion up to the steady state duty

cycle determined by the control loop. A plot of the LM3743

starting up into a pre-biased condition is shown in the Typical

Performance Characteristics section.

Note that the pre-bias voltage must not be greater than the

target output voltage of the LM3743, otherwise the LM3743

will pull the pre-bias supply down during steady state opera-

tion.

TRACKING WITH EQUAL SOFT-START TIME

The LM3743 can track the output of a master power supply

during soft-start by connecting a resistor divider to the SS/

TRACK pin. In this way, the output voltage slew rate of the

LM3743 will be controlled by the master supply for loads that

require precise sequencing. When the tracking function is

used, no soft-start capacitor should be connected to the

SS/TRACK pin. However in all other cases, a capacitor

value (C4) of at least 560 pF should be connected between

the soft-start pin and ground.

One way to use the tracking feature is to design the tracking

resistor divider so that the master supply’s output voltage

OUT1) and the LM3743’s output voltage (represented sym-

bolically in Figure 1 as V

OUT2, i.e. without explicitly showing

the power components) both rise together and reach their

target values at the same time. For this case, the equation

governing the values of the tracking divider resistors R

T1 and

T2 is:

The top resistance R

T2 must be set to 1 k

Ω in order to limit

current into the LM3743 during UVLO or shutdown. The final

voltage of the SS/TRACK pin should be slightly higher than

the feedback voltage of 0.8V, say about 0.85V as in the

above equation. The 50 mV difference will ensure the

LM3743 to reach regulation slightly before the master sup-

ply. If the master supply voltage was 5V and the LM3743

20177430

FIGURE 1. Tracking Circuit

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