LM3743 datasheet(17/23 Pages) NSC

17 / 23 page

Application Information (Continued)

Where duty cycleD=V

OUT/VIN. The worst-case ripple for a

buck converter occurs during full load and when the duty

cycle (D) is 0.5.

When multiple capacitors of the same type and value are

paralleled, the power dissipated by each input capacitor is:

where n is the number of paralleled capacitors, and ESR is

the equivalent series resistance of each capacitor. The equa-

tion above indicates that power loss in each capacitor de-

creases rapidly as the number of input capacitors increases.

For this 5V to 1.8V design the duty cycle is 0.36. For a 10A

maximum load the RMS current is 4.8A.

Connect one or two 22 µF MLCC as close as possible across

the drain of the high-side MOSFET and the source of the

low-side MOSFET, this will provide high frequency decou-

pling and satisfy the RMS stress. A bulk capacitor is recom-

mended in parallel with the MLCC in order to prevent switch-

ing frequency noise from reflecting back into the input line,

this capacitor should be no more than 1inch away from the

MLCC capacitors.

MOSFETs

Selection of the power MOSFETs is governed by a trade-off

between cost, size, and efficiency. One method is to deter-

mine the maximum cost that can be endured, and then

select the most efficient device that fits that price. Using a

spreadsheet to estimate the losses in the high-side and

low-side MOSFETs is one way to determine relative efficien-

cies between different MOSFETs. Good correlation between

the prediction and the bench result is not guaranteed.

Losses in the high-side MOSFET can be broken down into

conduction loss, gate charging loss, and switching loss.

Conduction, or I

2R loss, is approximately:

For the high side FET:

C =D(IOUT

2 xR

DSON-HI x 1.3)

For the low side FET:

C =(1-D)x(IOUT

2 xR

DSON-LO x 1.3)

In the above equations the factor 1.3 accounts for the in-

crease in MOSFET R

DSON due to heating. Alternatively, the

1.3 can be ignored and the R

DSON of the MOSFET estimated

using the R

DSON vs. Temperature curves in the MOSFET

manufacturer datasheet.

Gate charging loss results from the current driving the gate

capacitance of the power MOSFETs, and is approximated

as:

GC =(VCC)xQG xfSW

CC is the driving voltage (see MOSFET Gate Driver sec-

tion) and Q

G is the gate charge of the MOSFET. If multiple

devices will be placed in parallel, their gate charges can

simply be summed to form a cumulative Q

Switching loss occurs during the brief transition period as the

high-side MOSFET turns on and off, during which both cur-

rent and voltage are present in the channel of the MOSFET.

It can be approximated as:

SW =0.5xVIN xIOUT x(tr +tf)xfSW

where t

r and tf are the rise and fall times of the MOSFET.

Switching loss occurs in the high-side MOSFET only.

For this example, the maximum drain-to-source voltage ap-

plied to either MOSFET is 5.5V. The maximum drive voltage

at the gate of the high-side MOSFET is 5.0V, and the maxi-

mum drive voltage for the low-side MOSFET is 5.5V. For

designs between 5A and 10A, single MOSFETs in SO-8

provide a good trade-off between size, cost, and efficiency.

CC Filtering

To ensure smooth DC voltage for the chip supplya1µF

(C3), X5R MLCC type or better must be placed as close as

possible to the V

CC and GND pin. Together with a small 1 to

4.99

Ω resistor placed between the input rail and the V

CC pin,

a low pass filter is formed to filter out high frequency noise

from injecting into the V

CC rail. Since VCC is also the sense

pin for the high-side current limit, the resistor should connect

close to the drain of the high-side MOSFET to prevent IR

drops due to trace resistance. A second design consider-

ation is the low pass filter formed by C3 and R6 on the V

pin, a fast slew rate, large amplitude load transient may

cause a larger voltage droop on C

IN than on VCC pin. This

may lead to a lower current at which high-side protection

may occur. Thus increase the bulk input capacitor if the

high-side current limit is engaging due to a dynamic load

transient behavior as explained above.

Bootstrap Diode (D1)

The MBR0520 and BAT54 work well as a bootstrap diode in

most designs. Schottky diodes are the preferred choice for

the bootstrap circuit because of their low forward voltage

drop. For circuits that will operate at high ambient tempera-

ture the Schottky diode datasheet must be read carefully to

ensure that the reverse current leakage at high temperature

does not increase enough to deplete the charge on the

bootstrap capacitor while the high side FET is on. Some

Schottky diodes increase their reverse leakage by as much

as 1000 times at high temperatures. Fast rectifier and PN

junction diodes maintain low reverse leakage even at high

ambient temperature. These diode types have higher for-

ward voltage drop but can still be used for high ambient

temperature operation.

Control Loop Compensation

The LM3743 uses voltage-mode (‘VM’) PWM control to cor-

rect changes in output voltage due to line and load tran-

sients. VM requires careful small signal compensation of the

control loop for achieving high bandwidth and good phase

margin.

The control loop is comprised of two parts. The first is the

power stage, which consists of the duty cycle modulator,

output inductor, output capacitor, and load. The second part

is the error amplifier, which for the LM3743 is a 30 MHz

op-amp used in the classic inverting configuration. Figure 8

shows the regulator and control loop components.

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