MPC9352 REVISION 8 MARCH 14, 2016

5

©2016 Integrated Device Technology, Inc.

MPC9353 Data Sheet

3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR

Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to 85°C)

(1)

1. AC characteristics apply for parallel output termination of 50

 to V

TT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input reference frequency in PLL mode(2)

4 feedback

6 feedback

8 feedback

12 feedback

Input reference frequency in PLL bypass mode(3)

2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a

2 divider for feedback.

3. In PLL bypass mode, the MPC9352 divides the input reference clock.

50.0

33.3

25.0

16.67

100.0

66.6

50.0

33.3

250.0

MHz

MHz

MHz

MHz

MHz

fVCO

VCO lock frequency range(4)

4. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO  FB.

200

400

MHz

fMAX

Output Frequency

2 output(5)

4 output

6 output

8 output

12 output

5. See Table 9 and Table 10 for output divider configurations.

100

50

33.3

25

16.67

200

100

66.6

50

33.3

MHz

MHz

MHz

MHz

MHz

frefDC

Reference Input Duty Cycle

25

75

%

tr, tf

CCLK Input Rise/Fall Time

1.0

ns

0.8 to 2.0 V

t()

Propagation Delay CCLK to FB_IN

fref > 40 MHz

(static phase offset)

fref < 40 MHz

–50

–200

+150

+150

ps

ps

PLL locked

tsk(O)

Output-to-output Skew(6)

all outputs, any frequency

within QA output bank

within QB output bank

within QC output bank

6. See Applications Information section for part-to-part skew calculation.

200

200

100

100

ps

ps

ps

ps

DC

Output duty cycle

47

50

53

%

tr, tf

Output Rise/Fall Time

0.1

1.0

ns

0.55 to 2.4 V

tPLZ, HZ

Output Disable Time

8

ns

tPZL, LZ

Output Enable Time

10

ns

tJIT(CC)

Cycle-to-cycle jitter

output frequencies mixed

outputs are in any

4 and 6 combination

all outputs same frequency

400

250

100

ps

ps

ps

tJIT(PER)

Period Jitter

output frequencies mixed

outputs are in any

4 and 6 combination

all outputs same frequency

200

150

75

ps

ps

ps

tJIT()

I/O Phase Jitter

4 feedback divider RMS (1 )(7)

6 feedback divider RMS (1 )

8 feedback divider RMS (1 )

12 feedback divider RMS (1 )

7. See Applications Information section for a jitter calculation for other confidence factors than 1

.

15

20

18 – 20

25

ps

ps

ps

ps

BW

PLL closed loop bandwidth(8)

4 feedback

6 feedback

8 feedback

12 feedback

8. -3 dB point of PLL transfer characteristics.

3.0 – 10.0

1.5 – 6.0

1.0 – 3.5

0.5 – 2.0

MHz

MHz

MHz

MHz

tLOCK

Maximum PLL Lock Time

10

ms