MPC9352 REVISION 8 MARCH 14, 2016

7

©2016 Integrated Device Technology, Inc.

MPC9353 Data Sheet

3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR

APPLICATIONS INFORMATION

Programming the MPC9352

The MPC9352 supports output clock frequencies from

16.67 to 200 MHz. Different feedback and output divider

configurations can be used to achieve the desired input to

output frequency relationship. The feedback frequency and

divider should be used to situate the VCO in the frequency

lock range between 200 and 400 MHz for stable and optimal

operation. The FSELA, FSELB, FSELC pins select the

desired output clock frequencies. Possible frequency ratios

of the reference clock input to the outputs are 1:1, 1:2, 1:3,

3:2 as well as 2:3, 3:1 and 2:1. Table 9 and Table 10

illustrates the various output configurations and frequency

ratios supported by the MPC9352. See also Figure 3 to

Figure 6 for further reference. A 2 output divider cannot be

used for feedback.

tJIT()

I/O Phase Jitter

4 feedback divider RMS (1 )(7)

6 feedback divider RMS (1 )

8 feedback divider RMS (1 )

12 feedback divider RMS (1 )

15

20

18 – 20

25

ps

ps

ps

ps

BW

PLL closed loop bandwidth(8)

4 feedback

6 feedback

8 feedback

12 feedback

1.0 – 8.0

0.7 – 3.0

0.5 – 2.5

0.4 – 1.0

MHz

MHz

MHz

MHz

tLOCK

Maximum PLL Lock Time

10

ms

1. AC characteristics apply for parallel output termination of 50

 to V

TT.

2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a

2 divider for feedback.

3. In PLL bypass mode, the MPC9352 divides the input reference clock.

4. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO  FB.

5. See Table 9 and Table 10 for output divider configurations.

6. See application section for part-to-part skew calculation.

7. See application section for a jitter calculation for other confidence factors than 1

.

8. -3 dB point of PLL transfer characteristics.

Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)

(1) (Continued)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Table 9. MPC9352 Example Configuration (F_RANGE = 0)

PLL

Feedback

fref(1) [MHz]

1. fref is the input clock reference frequency (CCLK).

FSELA

FSELB

FSELC

QA[0:4]:fref ratio

QB[0:3]:fref ratio

QC[0:1]:fref ratio

VCO

 4(2)

2. QAx connected to FB_IN and FSELA=0.

50-100

0

0

0

fref

(50-100 MHz)

fref

(50-100 MHz)

fref * 2 (100-200 MHz)

0

0

1

fref

(50-100 MHz)

fref

(50-100 MHz)

fref

(50-100 MHz)

1

0

0

fref * 2

3 (33-66 MHz) fref

(50-100 MHz)

fref * 2 (100-200 MHz)

1

0

1

fref * 2

3 (33-66 MHz) fref

(50-100 MHz)

fref

(50-100 MHz)

VCO

 6(3)

3. QAx connected to FB_IN and FSELA=1.

33.3-66.67

1

0

0

fref

(33-66 MHz)

fref * 3

2 (50-100 MHz) fref * 3 (100-200 MHz)

1

0

1

fref

(33-66 MHz)

fref * 3

2 (50-100 MHz) fref * 32 (50-100 MHz)

1

1

0

fref

(33-66 MHz)

fref * 3 (100-200 MHz)

fref * 3 (100-200 MHz)

1

1

1

fref

(33-66 MHz)

fref * 3 (100-200 MHz)

fref * 3

2 (50-100 MHz)