MPC9352 datasheet(8/17 Pages) RENESAS

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MPC9352 REVISION 8 MARCH 14, 2016

MPC9353 Data Sheet

3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR

Table 10. MPC9352 Example Configurations (F_RANGE = 1)

PLL Feedback

fref(1) [MHz]

1. fref is the input clock reference frequency (CCLK).

FSELA

FSELB

FSELC

QA[0:4]:fref ratio

QB[0:3]:fref ratio

QC[0:1]:fref ratio

VCO

 8(2)

2. QAx connected to FB_IN and FSELA=0.

25-50

fref

(25-50 MHz)

fref

(25-50 MHz)

fref * 2

(50-100 MHz)

fref

(25-50 MHz)

fref

(25-50 MHz)

fref

(25-50 MHz)

fref * 2

3 (16-33 MHz) fref

(25-50 MHz)

fref * 2

(50-100 MHz)

fref * 2

3 (16-33 MHz) fref

(25-50 MHz)

fref

(25-50 MHz)

VCO

 12(3)

3. QAx connected to FB_IN and FSELA=1.

16.67-33.3

fref

(16-33 MHz)

fref * 3

2 (25-50 MHz) fref * 3 (50-100 MHz)

fref

(16-33 MHz)

fref * 3

2 (25-50 MHz) fref * 32 (25-50 MHz)

fref

(16-33 MHz)

fref * 3

(50-100 MHz)

fref * 3

(50-100 MHz)

fref

(16-33 MHz)

fref * 3

(50-100 MHz)

fref * 3

2 (25-50 MHz)

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