Electronic Components Datasheet Search
  English  ▼

X  

MPC9352 Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # MPC9352
Description  3.3V/2.5V 1:11 LVCMOS Zero Delay Clock Generator
PDF  17 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

MPC9352 Datasheet(HTML) 9 Page - Renesas Technology Corp

Back Button MPC9352 Datasheet HTML 5Page - Renesas Technology Corp MPC9352 Datasheet HTML 6Page - Renesas Technology Corp MPC9352 Datasheet HTML 7Page - Renesas Technology Corp MPC9352 Datasheet HTML 8Page - Renesas Technology Corp MPC9352 Datasheet HTML 9Page - Renesas Technology Corp MPC9352 Datasheet HTML 10Page - Renesas Technology Corp MPC9352 Datasheet HTML 11Page - Renesas Technology Corp MPC9352 Datasheet HTML 12Page - Renesas Technology Corp MPC9352 Datasheet HTML 13Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 17 page
background image
MPC9352 REVISION 8 MARCH 14, 2016
9
©2016 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
MPC9352 configuration to multiply the reference
frequency by 3, 3
 2 and 1. PLL feedback of
QA4 = 33.3 MHz.
Figure 4. MPC9352 Zero Delay Buffer Configuration
Figure 5. MPC9352 Default Configuration
Figure 6. MPC9352 Zero Delay Buffer
Configuration 2
MPC9352
fref = 100 MHz
100 MHz
100 MHz
100 MHz (Feedback)
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELD
F_RANGE
200 MHz
MPC9352 default configuration (feedback of QB0 = 100 MHz).
All control pins are left open.
MPC9352
fref = 62.5 MHz
62.5 MHz
62.5 MHz
62.5 MHz (Feedback)
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELC
F_RANGE
62.5 MHz
MPC9352 zero-delay (feedback of QB0 = 62.5 MHz). All
control pins are left open except FSELC = 1. All outputs
are locked in frequency and phase to the input clock.
MPC9352
fref = 33.3 MHz
33.3 MHz
50 MHz
33.3 MHz (Feedback)
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELC
F_RANGE
100 MHz
MPC9352
fref = 33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz (Feedback)
QA0
QA1
QA2
QA3
QQ4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELC
F_RANGE
33.3 MHz
MPC9352 zero-delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Frequency Range
Min
Max
Input
50 MHz
100 MHz
QA outputs
50 MHz
10 MHz
QB outputs
50 MHz
100 MHz
QC outputs
100 MHz
200 MHz
Frequency Range
Min
Max
Input
50 MHz
100 MHz
QA outputs
50 MHz
10 MHz
QB outputs
50 MHz
100 MHz
QC outputs
50 MHz
100 MHz
Frequency Range
Min
Max
Input
25 MHz
50 MHz
QA outputs
50 MHz
10 MHz
QB outputs
50 MHz
100 MHz
QC outputs
100 MHz
200 MHz
Frequency Range
Min
Max
Input
25 MHz
50 MHz
QA outputs
25 MHz
50 MHz
QB outputs
25 MHz
50 MHz
QC outputs
25 MHz
50 MHz
VCC
VCC
VCC
VCC
VCC
VCC
Figure 3. MPC9352 Default Configuration
Example Configurations for the MPC9352



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com