X5643P datasheet(7/19 Pages) RENESAS

7 / 19 page

X5643, X5645 (Replaces X25643, X25645)

FN8135 Rev 1.00

Page 7 of 19

July 18, 2005

Figure 5. Read EEPROM Array Sequence

Setting the WP pin LOW while WPEN is a “1” while an

internal write cycle to the status register is in progress

will not stop this write operation, but the operation dis-

ables subsequent write attempts to the status register.

When WP is HIGH, all functions, including nonvolatile

writes to the status register operate normally. Setting the

WPEN bit in the status register to “0” blocks the WP pin

function, allowing writes to the status register when WP

is HIGH or LOW. Setting the WPEN bit to “1” while the

WP pin is LOW activates the programmable ROM mode,

thus requiring a change in the WP pin prior to subse-

quent status register changes. This allows manufactur-

ing to install the device in a system with WP pin

grounded and still be able to program the status register.

Manufacturing can then load configuration data, manu-

facturing time and other parameters into the EEPROM,

then set the portion of memory to be protected by setting

the block lock bits, and finally set the “OTP mode” by

setting the WPEN bit. Data changes now require a hard-

ware change.

Read Sequence

When reading from the EEPROM memory array, CS is first

pulled low to select the device. The 8-bit READ instruction is

transmitted to the device, followed by the 16-bit address.

After the READ opcode and address are sent, the data

stored in the memory at the selected address is shifted out

on the SO line. The data stored in memory at the next

address can be read sequentially by continuing to provide

clock pulses. The address is automatically incremented to

the next higher address after each byte of data is shifted out.

When the highest address is reached, the address counter

rolls over to address $0000 allowing the read cycle to be

continued indefinitely. The read operation is terminated by

taking CS high. Refer to the read EEPROM array sequence

(Figure 1).

To read the status register, the CS line is first pulled low to

select the device followed by the 8-bit RDSR instruction.

After the RDSR opcode is sent, the contents of the status

status register sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the

“Write Enable” Latch (WEL) must first be set by issuing

the WREN instruction (Figure 3). CS is first taken LOW,

then the WREN instruction is clocked into the device.

After all eight bits of the instruction are transmitted, CS

must then be taken HIGH. If the user continues the write

operation without taking CS HIGH after issuing the WREN

instruction, the write operation will be ignored.

To write data to the EEPROM memory array, the user

then issues the WRITE instruction followed by the 16 bit

address and then the data to be written. Any unused

address bits are specified to be “0’s”. The WRITE opera-

tion minimally takes 32 clocks. CS must go low and

remain low for the duration of the operation. If the

address counter reaches the end of a page and the

clock continues, the counter will roll back to the first

address of the page and overwrite any data that may

have been previously written.

For the page write operation (byte or page write) to be

completed, CS can only be brought HIGH after bit 0 of

the last data byte to be written is clocked in. If it is

brought HIGH at any other time, the write operation will

not be completed (Figure 4).

To write to the status register, the WRSR instruction is

followed by the data to be written (Figure 5). Data bits 0

and 1 must be “0”.

20 21 22 23 24 25 26 27 28 29 30

543

Data Out

SCK

MSB

High Impedance

Instruction

16 Bit Address

15 14 13

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