X5643P datasheet(8/19 Pages) RENESAS

8 / 19 page

X5643, X5645 (Replaces X25643, X25645)

FN8135 Rev 1.00

Page 8 of 19

July 18, 2005

While the write is in progress following a status register or

EEPROM sequence, the status register may be read to

check the WIP bit. During this time the WIP bit will be high.

OPERATIONAL NOTES

The device powers-up in the following state:

– The device is in the low power standby state.

– A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

– SO pin is high impedance.

– The write enable latch is reset.

– The flag bit is reset.

– Reset signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– A WREN instruction must be issued to set the write

enable latch.

–CS must come HIGH at the proper clock count in order

to start a nonvolatile write cycle.

Figure 6. Read Status Register Sequence

Figure 7. Write Enable Latch Sequence

012

345

678

9 10 11 12 13 14

654

321

Data Out

SCK

MSB

High Impedance

Instruction

123

456

SCK

High Impedance

X5643P Datasheet(PDF) 8 Page - Renesas Technology Corp