ZSSC4151C Datasheet

© 2022 Renesas Electronics Corporation

18

March 25, 2020

Recommendation: To achieve the best stability and linearity performance of the AFE, operate the PGA in a differential output voltage range

within 10% to 90% of the ratiometric reference voltage VREF = VSENS = (VTOP – VBOT). The gain must be selected to guarantee this constraint for

the entire operating temperature range of the application and for the specified sensor bridge tolerances.

7.3.5 Analog-to-Digital Converter

The analog-to-digital converter is implemented using the full-differential switched-capacitor technique. The conversion is largely insensitive to

short-term and long-term instabilities of the clock frequency. The ADC provides adjustability for the A/D conversion input voltage range shift.

7.4 Signal Conditioning

7.4.1 Full Bridge Sensor Signal Conditioning

The full-bridge sensor element signal conditioning uses ROM-resident formulas and sensor-element-specific coefficients stored in NVM. The

calculation is processed every time that a new measurement result value is available from the analog-to-digital conversion. The conditioning

calculation provides compensation of the temperature-dependent offset and gain and of the nonlinearity. All temperature sources can be

selected for the conditioning calculation of the full-bridge sensor element signal.

The conditioning coefficients are stored as signed 16-bit values (sint16, two’s complement) whereas the weights are stored as unsigned 4-bit

values (uint4) in the NVM during the calibration process.

All intermediate results and the final conditioning results for the full-bridge are stored as signed 16-bit values (sint16, two’s complement) in the

RAM output memory.

7.4.2 Conditioning Cycle

The conditioning cycle is the sequence of equations and supervision functions processed during the Normal Operation Mode (NOM). It uses

raw measurement results from measurement cycle and delivers conditioned output data for the analog output function.

7.5 Output Stage

The analog output is used for outputting the analog signal conditioning result and for “end of line” communication via the ZACwire™ interface

one-wire communication interface (OWI). The ZSSC4151C supports four different modes of the analog output in combination with the OWI

behavior:



AOUT_CYC_OWI_DIS: Analog output will be activated after a ~7ms power on time. OWI is disabled. Only I2C communication is possible.



AOUT_CYC: Analog output will be activated after a ~7ms power on time. OWI communication is enabled for a time window of ~250ms.

Transmission of the START_CM command must occur during the time window in order to activate the Command Mode. For

communication, the internal driven potential at AOUT must be overwritten by the external communication master (AOUT drive capability is

current limited).



AOUT_WIN: Analog output will be activated after the OWI start time window. OWI communication is enabled for a time window of

~250ms. Transmission of the “START_CM” command must occur during the time window.



OWI: Analog output is deactivated; OWI communication is enabled.

The analog output potential is driven by a unity gain output buffer for which the input signal is generated by a 12-bit resistor-string DAC. The

output buffer, which is a rail-to-rail op amp, is offset compensated and current limited. Therefore, a short-circuit of the analog output to ground

or the power supply does not damage the ZSSC4151C.