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AD7401 Datasheet(PDF) 4 Page - Analog Devices |
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AD7401 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 20 page  AD7401 Rev. 0 | Page 4 of 20 TIMING SPECIFICATIONS1 VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter Limit at TMIN, TMAX Unit Description fMCLKIN2 16 MHz max Master clock input frequency 5 MHz min Master clock input frequency t13 25 ns max Data access time after MCLK rising edge t23 15 ns min Data hold time after MCLK rising edge t3 0.4 × tMCLKIN ns min Master clock low time t4 0.4 × tMCLKIN ns min Master clock high time 1 Sample tested during initial release to ensure compliance. 2 Mark space ratio for clock output is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 25pF Figure 2. Load Circuit for Digital Output Timing Specifications MCLKIN MDAT t1 t2 t4 t3 Figure 3. Data Timing |
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