AMC131M03 datasheet(39/90 Pages) TI

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DRDY

SCLK

DIN

DOUT

Channel 0 Data

Channel 1 Data

Channel 2 Data

CRC

Response

Hi-Z

Channel 0 Data

Response

Command

CRC

Command

CRC

Figure 8-24. Typical Communication Frame

There are some commands that require more than five words. In the case of a read register (RREG) command

where multiple registers are read, the response to the command contains the acknowledgment of the command

followed by the register contents requested, which can require a larger frame depending on how many registers

are read. See the RREG section for more details on the RREG command.

In the case of a write register (WREG) command where multiple registers are written, the frame extends to

accommodate the additional data. See the WREG section for more details on the WREG command.

See the Commands section for a list of all valid commands and the corresponding responses on the

AMC131M03-Q1.

Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for

more information about artificially shortening communication frames.

8.5.1.8 SPI Communication Words

An SPI communication frame with the AMC131M03-Q1 is made of words. Words on DIN can contain

commands, register settings during a register write, or a CRC of the input data. Words on DOUT can contain

command responses, register settings during a register read, ADC conversion data, or the CRC of the output

data.

Words can be 16, 24, or 32 bits. The word size is configured by the WLENGTH[1:0] bits in the MODE register.

The device defaults to a 24-bit word size. Commands, responses, CRC, and registers always contain 16 bits

of actual data. These words are always most significant bit (MSB) aligned, and therefore the least significant

bits (LSBs) are zero-padded to accommodate 24- or 32-bit word sizes. ADC conversion data are nominally 24

bits. The ADC truncates the eight LSBs when the device is configured for 16-bit communication. There are two

options for 32-bit communication available for ADC data that are configured by the WLENGTH[1:0] bits in the

MODE register. Either the ADC data can be LSB padded with zeros or the data can be MSB sign extended.

8.5.1.9 Short SPI Frames

The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and

no ADC data are being output by the device. Read out all expected output data words from each sample period

if the ADCs are enabled. Reading all data output with each frame ensures predictable DRDY pin behavior. If

reading out all data on each output data period is not feasible, see the Collecting Data for the First Time or After

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AMC131M03-Q1

SBASAO3 – MAY 2023

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