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AMC131M03 Datasheet(PDF) 21 Page - Texas Instruments |
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AMC131M03 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 90 page  bandwidth results in lower noise, whereas higher bandwidth results in higher noise. See Table 7-1 for the noise specifications for various OSR settings. Table 8-4. OSR Settings and Data Rates for Nominal Controller Clock Frequencies POWER MODE NOMINAL CONTROLLER CLOCK FREQUENCY fMOD(1) OSR OUTPUT DATA RATE High-resolution (HR) 8.192 MHz 4.096 MHz 64 64 kSPS 128 32 kSPS 256 16 kSPS 512 8 kSPS 1024 4 kSPS 2048 2 kSPS 4096 1 kSPS 8192 500 SPS 16384 250 SPS Low-power (LP) 4.096 MHz 2.048 MHz 64 32 kSPS 128 16 kSPS 256 8 kSPS 512 4 kSPS 1024 2 kSPS 2048 1 kSPS 4096 500 SPS 8192 250 SPS 16384 125 SPS (1) Programmable clock divider is set to NDIV = 2. 8.3.11.1 Digital Filter Implementation Figure 8-6 shows the digital filter implementation of the AMC131M03-Q1. The modulator bitstream feeds two parallel filter paths: a sinc3 filter and a fast-settling filter path. Modulator Bitstream Sinc 3 Regular Filter Fast-Settling Filter Sinc 1 Averager (OSR > 1024) Global Chop Logic PHASEx[9:0] PGA_GAINx[2:0] OSR 1024 Power-up or Reset MUX MUX 1 0 1 0 Calibration Logic, Gain scaling OSR = 1024 OSR[2:0] OSR[2:0] Phase Delay Figure 8-6. Digital Filter Implementation 8.3.11.1.1 Fast-Settling Filter At power-up or after a device reset, the AMC131M03-Q1 selects the fast-settling filter to allow for settled output data generation with minimal latency. The fast-settling filter has the characteristic of a first-order sinc filter (sinc1). After two conversions, the device switches to and remains in the sinc3 filter path until the next time the device is powered down or reset. www.ti.com AMC131M03-Q1 SBASAO3 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: AMC131M03-Q1 |
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