AT75C datasheet(7/171 Pages) ATMEL

7 / 171 page

AT75C DSP Subsystem

1368C–INTAP–08/02

Product Output Shifter

The register P is sign-extended into 36 bits and then shifted. In addition to passing the

data unshifted, the output shifter is capable of shifting the data from the register P into

the ALU unit by one bit to the right or by one and two bits to the left. In right shift, the

sign is extended, whereas in left shift, a zero is appended to the LSBs. Shift operation is

controlled by two bits (PS) in the status register ST1. The shifter also includes alignment

(a 16-bit right shift) for supporting double-precision multiplication.

Double-precision Multiplication

The OakDSPCore supports double-precision multiplication by several multiplication

instructions and by alignment option of the register P. The register P can be aligned

(shifting 16 bits to the right) before accumulating the partial multiplication results, in mul-

tiply-accumulate instructions (MAA and MAASU instructions). An example of different

multiplication operations is in the multiplication of 32-bit by 16-bit fractional numbers,

where two multiplication operations are needed: multiplying the 16-bit number with the

lower or upper portion of a 32-bit (double-precision) number. The signed-by-unsigned

operation is used to multiply or multiply-accumulate the 16-bit signed number with the

lower, unsigned portion of the 32-bit number. The signed-by-signed operation is used to

multiply the 16-bit signed number with the upper, signed portion of the 32-bit number.

While the signed-by-signed operation is executed, it is recommended to accumulate the

aligned (using MAA instruction) result of the previous signed-by-unsigned operation. For

the multiplication of two double-precision (32-bit) numbers, the unsigned operation can

be used. If this operation requires a 64-bit result, the unsigned-by-unsigned operation

should be used. For details, on the various multiply instructions (MPY, MPYSU,

MACUS, MACUU, MAA, MAASU, MSU and MPYI), refer to “Instruction Set” on page 31.

Ax-accumulators

Each Ax-accumulator is organized as two regular 16-bit registers (A0H, A0L, A1H and

A1L) and a 4-bit extension nibble (A0E and A1E). The two portions of each accumulator

can be accessed as any other 16-bit data register and can be used as 16-bit source or

destination registers in all relevant instructions. The Ax-accumulators can serve as the

source operand and the destination operand of the ALU, barrel shifter and exponent

units. The extension nibbles of the A0 and A1 accumulators are the MSB’s part of status

registers ST0 and ST1, respectively. The Ax-accumulators can be swapped with the Bx-

accumulators in a single cycle. Saturation arithmetic is provided to selectively limit over-

flow from the high portion of an accumulator to the extension bits when performing a

move instruction from one of the accumulators through the XDB, or when using the LIM

instruction, which performs saturation on the 36-bit accumulator. For more details, refer

to “Saturation” on page 12.

Registers AxH and AxL can also be used as general-purpose, temporary 16-bit data

registers.

Extension Nibbles

Extension nibbles A0E and A1E offer protection against 32-bit overflows. When the

result of an ALU output crosses bit 31, it sets the extension flag (E) in ST0, representing

crosses of the MSB in AxH. Up to 15 overflows or underflows are possible using the

extension nibble, after which the sign is lost beyond the MSB of the ALU output and/or

beyond the MSB of the extension nibble, setting the overflow flag (V) in ST0, and also

latching the Limit flag (L) in ST0. Refer to “Status Registers” on page 23 for more detail.

Sign Extension

Sign extension of the 36-bit Ax-accumulators is provided when the Ax or AxH is written

with a smaller size operand. This occurs when these registers are written from XDB,

from the ALU or from the exponent unit in certain CBU operations. Sign extension can

be suppressed by specific instructions. For details, refer to “Instruction Set” on page 31.

Loading of Ax-accumulators

AxL is cleared while loading data into AxH, and AxH is cleared while loading AxL. Load-

ing a full 32-bit value is accomplished via the ADDL or ADDH instructions (refer to

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