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AT75C Datasheet(PDF) 35 Page - ATMEL Corporation |
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AT75C Datasheet(HTML) 35 Page - ATMEL Corporation |
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35 / 171 page ![]() 35 AT75C DSP Subsystem 1368C–INTAP–08/02 contents of the P register remain unchanged. At two multiply instructions, maa and maasu, the P register is also aligned, i.e., after the P register is sign- extended and shifted according to the PS field, it is also shifted by 16 to the right. 6. All move instructions using the accumulator (aX or bX) as a destination are sign- extended. All instructions that use the accumulator-low (aXl or bXl) as a destination will clear the accumulator-high and the accumulator extension. Therefore, they are sign extension-suppressed. All instructions using the accumulator-high (aXh or bXh) as a destination will clear the accumulator-low and are sign- extended. An exception is mov direct address, axh [eu], when moving data into accumulator-high can be controlled with sign exten- sion or with sign extension unaffected (the accumulator extension aXe is unaffected). 7. In all arithmetic operations between 16-bit registers and aX (36 bits), the 16-bit register will be regarded as the 16 low-order bits of a 36-bit operand with a sign extension in the MSBs. 8. It is recommended that the flags are used immediately after the instruction that updated them. Otherwise, very careful programming is required (some flags may be changed in the meantime). 9. The condition field is almost always an optional field, except when the condition is followed by another optional field as in reti instruction. The condition field is the last field of the instruction. When the condition field is missing, the condition is true. Examples: shr4 true is the same as shr4, but in reti true, context the true cannot be omitted. 10. General Restrictions: a) Arithmetic and logical operations (but not bit-manipulation operations) must not be performed with the same accumulator as the source (soperand) and the destina- tion (doperand). Example: add a0, a0 is not allowed (shfc a0, a0 is allowed) b) An instruction immediately following an instruction that modifies the rb register may not use the index addressing mode. The only exception is when rb is modified using a long immediate operand (mov ## long immediate, rb). 11. Two nop instructions should follow instructions that use the pc as a destination register except after move ## long immediate, pc, where only one nop is needed. |
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