LM3880 datasheet(17/20 Pages) NSC

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located a distance of not more than 1 cm from the V

IN_LILO

input pin and returned to QGND.

IN_LDO

An input capacitor is required for stability. It is recommended

to use a 1 µF ceramic capacitor and connected between the

IN_LDO and QGND.

Output Capacitor

OUT_DCDC

A ceramic output capacitor of 10 µF, 6.3V is sufficient for most

applications. Use X7R or X5R types; do not use Y5V. DC bias

characteristics of ceramic capacitors must be considered

when selecting case sizes like 0805 and 0603. DC bias char-

acteristics vary from manufacturer to manufacturer and dc

bias curves should be requested from them as part of the ca-

pacitor selection process.

The minimum output capacitance to guarantee good per-

formance is 5.75 µF at 1.8V DC bias including tolerances

and over ambient temperature range. The output filter ca-

pacitor smooths out current flow from the inductor to the load,

helps maintain a steady output voltage during transient load

changes and reduces output voltage ripple. These capacitors

must be selected with sufficient capacitance and sufficiently

low ESR to perform these functions.

The output voltage ripple is caused by the charging and dis-

charging of the output capacitor and by the R

ESR and can be

calculated as:

Voltage peak-to-peak ripple due to capacitance can be ex-

pressed as follow:

Voltage peak-to-peak ripple due to ESR can be expressed as

follow:

PP-ESR = (2*IRIPPLE) * RESR

Because these two components are out of phase, the rms

(root mean squared) value can be used to get an approximate

value of peak-to-peak ripple. The peak-to-peak ripple voltage,

rms value can be expressed as follow:

Note that the output voltage ripple is dependent on the induc-

tor current ripple and the equivalent series resistance of the

output capacitor (R

ESR). The RESR is frequency dependent (as

well as temperature dependent); make sure the value used

for calculations is at the switching frequency of the part.

OUT_LILO

The linear regulator is designed specifically to work with very

small ceramic output capacitors. A ceramic capacitor (dielec-

tric types X7R, Z5U, or Y5V) in the 2.2 µF range (up to 10 µF)

and with an ESR between 3 m

Ω to 300 mΩ is suitable as

OUT_LIN in the LM3686 application circuit.

This capacitor must be located a distance of not more than

1cm from the V

OUT_LILO pin and returned to a clean analogue

ground. It is also possible to use tantalum or film capacitors

at the device output, V

OUT_LILO but these are not as attractive

for reasons of size and cost (see the section Capacitor Char-

acteristics).

OUT_LDO

A ceramic capacitor in the 1 uF to 2.2 uF range, and with ESR

between 5 m

Ω to 500 mΩ, is suitable for the linear regulator.

This output capacitor should be connected no more than 1 cm

from V

OUT_LDO and QGND

30025508

FIGURE 8. Graph Showing a Typical Variation In

Capacitance vs. DC Bias

TABLE 2. Suggested Capacitors and their Suppliers

Capacitance / µF

Model

Voltage Rating

Vendor

Type

Case Size / Inch (mm)

10.0

C1608X5R0J106K

6.3V

TDK

Ceramic, X5R

0603 (1608)

4.7

C1608X5R0J475

6.3V

TDK

Ceramic, X5R

0603 (1608)

2.2

C1608X5R0J225M

6.3V

TDK

Ceramic, X5R

0603 (1608)

1.0

C1005JB0J105KT

6.3V

TDK

Ceramic, X5R

0402 (1005)

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