ATA6621 datasheet(14/26 Pages) ATMEL

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4887B–AUTO–01/06

ATA6621

After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES

stays low for the time t

reset (typically 10 ms), then it switches to high and the watchdog waits for

the watchdog sequence from the microcontroller. This lead time t

d follows after the reset and is

d = 49 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger

pulse NTRIG (or PTRIG, as the case may be) occurs during this time, the time t

1 starts immedi-

ately. If no trigger signal occurs during the time t

d, a watchdog reset with tNRES = 1.96 ms will

reset the microcontroller after t

d = 49 ms. The times t1 and t2 have a fixed relationship with each

other. A triggering signal from the microcontroller is anticipated within the time frame of

2 = 10.5 ms. To avoid false triggering from glitches, the trigger pulse must be longer than

trigg > 3 µs. This slope serves to restart the watchdog sequence. Should the triggering signal fail

in this open window t

2, the NRES output will be drawn to ground after t2. A triggering signal dur-

ing the closed window t

1 causes NRES to immediately switch low.

Figure 3-8.

Timing Sequence with R

WD_OSC = 51 kΩ

3.16.2

Worst Case Calculation with R

WO_OSC = 51 kΩ

The internal oscillator has a tolerance of ±20%. This means that t

1 and t2 can also vary by ±20%.

The worst case calculation for the watchdog period T

wd the microcontroller has to provide is cal-

culated as follows.

The ideal watchdog time T

wd is between (t1maximum) and (t1 minimum plus t2 minimum).

1,min = 0.8 × t1 = 8 ms, t1,max = 1.2 × t1 = 12 ms

2,min = 0.8 × t2 = 8.4 ms, t2,max = 1.2 × t2 = 12.6 ms

wdmax = t1min + t2min = 8 ms + 8.4 ms = 16.4 ms

wdmin = t1max = 12 ms

wd = 14.2 ms ±2.2 ms (±15%)

A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs

correctly within the time period of T

wd = 14.2 ms (±15%) in an application with Rwd_osc = 51 kΩ.

tnres = 1.9 ms

Undervoltage Reset

Watchdog Reset

treset = 10 ms

t1 = 10 ms

ttrigg > 3 µs

t2 = 10.5 ms

twd

td = 49 ms

VCC = 5V

PTRIG

NTRIG

NRES

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