30 Pin Descriptions

Symbol

Pin No

IO

Description

8

I

4B5B serial NRZI data inputs originating from a fiber optic receiver and presented for

the purpose of resynchronization and clock recovery These differential 100k ECL compatible

9

inputs are selected when the ELB input is at a logic Low level

25

I

4B5B serial NRZI data inputs originating from a local PLAYER device and

presented for the purpose of station diagnostics These differential 100k ECL compatible inputs

24

are selected when the ELB input is at a logic High level

ELB

4

I

Enable Loopback

g

inputs The LBD inputs are selected when the ELB pin is at a logic High level and the DATA

inputs when at a logic Low level

CLK DET

6

O

Clock Detect

CMOS output used to indicate that the chip has detected the presence of a

continuous data frequency greater than 30 MHz A logic High level on the output will indicate that

valid input data has been detected

CRD EN

7

I

CRD Enable

TTL compatible input which directs the differential charge pump outputs to either

operate the crystal oscillator at the center of its operating range or to track out the VCO phase

errors in the second PLL The CRD EN input will reset the CLK DET function and will force the

oscillator to the center of its operating range when at a logic LOW level and will allow normal PLL

tracking operation when at a logic High level Deassertion of the CRD EN input will momentarily

stop the VCO

23

O

The differential charge pump up and down outputs which are part of the

second PLL A three element filter should be connected to each of these pins which consists of

22

one capacitor in parallel with a resistor and another capacitor to ground These outputs are driven

to their maximum upper operating level when the CRD EN pin is at a logic LOW level or when

valid data frequencies are not recognized at the data inputs

DIF AMP

21

O

Differential Amplifier Output

The differential amplifier output associated with the second PLL

which is used to adjust the frequency of the external crystal

OUT

OSC

IN

20

I

Oscillator Input and Output

The terminals for the crystal oscillator which require connection of

the crystal tank circuit varactors and capacitors

OSC

OUT

19

3

O

Receive Clock

Differential 100K ECL receive clock outputs which operate at 125 MHz

2

present When valid line state data is not present these outputs continue to operate at a nominal

conventional ECL 50X equivalent load

27

O

Receive Data

Differential 100K ECL received data outputs which provide a resynchronized

equivalent of the selected NRZI DATA or LBD inputs The received data output transitions occur

26

externally with a conventional ECL 50X equivalent load

VCO FLTR

13

O

VCO Filter

Low pass filter associated with the first PLL A three element filter should be

connected to this pin which consists of one capacitor in parallel with a resistor and another

capacitor to ground

18

I

Signal Detect

Differential inputs to a 100K ECL to TTL translator intended for conversion of the

fiber optic receiver’s ECL signal detect to TTL for a player device The inputs are used in the test

17

modes as inputs for single stepping and gating the VCO

TTLSD

5

O

TTL Signal Detect

Intended to be a signal detect output in TTL format for use by the PLAYER

chip

TEST EN

10

I

Test Enable

CMOS input which enables the test functions This input must be at a logic low level

in normal operation

16

chokes

6