DP83222 datasheet(2/12 Pages) NSC

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10 Functional Description

11 OVERVIEW

The DP83222 Stream Cipher ScramblerDescrambler De-

vice consists of 7 major functional blocks as shown in

Fig-

ure 1

The Scrambler section is comprised of an Encoder a De-

coder a linear Feedback Shift Register with support gates

and the Control Logic block The Decoder accepts synchro-

nous differential clock and data (data can be either NRZ or

NRZI formatted) from the Physical Layer and delivers NRZ

data to the 11-bit LFSR block

The LFSR scrambler and support gates exclusive-OR the

incoming unscrambled data stream with the resultant data

stream of the LFSR This data becomes the scrambled data

stream The Encoder accepts scrambled data from the

11-bit LFSR block and delivers either NRZ or NRZI asyn-

chronous data to the external PMD Transceiver

The Control Logic block functions as the EncodeDecode

switch selecting NRZ or NRZI formats and also controls

the disabling of the scrambler for use in transparent mode

The Descrambler section is comprised of an Encoder a De-

coder the Descrambler Logic block and the Control Logic

block (shared with the Scrambler section) The Encoder and

Decoder blocks work in conjunction with the corresponding

blocks within the Scrambler section A truth table describing

the available encodedecode format algorithms can be

found in Table II

The Stream Cipher Logic functions as a ‘‘Sample and Hold’’

state machine that when in sample mode continuously

evaluates incoming words by searching for identifiable FDDI

line states When valid line states are detected the Stream

Cipher enters the hold state During the hold state an 11-bit

LFSR operates to descramble the incoming data completing

the translation A more in-depth analysis of the stream ci-

pher algorithm is given in Section 13

The descrambled data is accompanied by a time aligned

version of the descramble clock allowing for synchronous

delivery of the data to the Physical Layer device

Finally the Control Logic block which is shared by both the

Scramble and Descramble sections controls several func-

tions The EncodeDecode switch controls the selection of

NRZ or NRZI conversion as well as the transparent mode of

operation Clock Detect (CD) and Signal Detect (SD) inputs

also part of the Control Logic block control certain stream

cipher logic modes

12 DATA SCRAMBLING

A more in-depth analysis of the scrambler function as illus-

trated in

Figure 2 reveals a fairly elementary design The

scrambler logic requires that the incoming data be NRZ for-

matted which the DP83222 accomplishes via the input de-

coder After being decoded to NRZ the data UD is routed

to one input of the Exclusive OR gate XOR-A The other

input to XOR-A is connected to the output of a closed loop

11-bit Linear Feedback Shift Register (LFSR)

ed to another XOR function XOR-B is performed The re-

sult of XOR-B LDS is then routed to the input of Register S

(this circuit forms a linear feedback shift register LFSR)

LDS is also routed to the other input of XOR-A which in

turn outputs the final scrambled data stream SD The data

sequences shown in

Figure 2 are defined as

UD e Unscrambled Data (originating from PHY)

LDS e Scrambler LFSR Feedback data

SD e (LFSR

S xor UD)

TLF11885 – 2

FIGURE 2 Stream Cipher Scrambler Logic

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