DP83222 datasheet(6/12 Pages) NSC

6 / 12 page

30 Pin Definitions and Connection Diagrams (Continued)

TLF11885 – 5

TLF11885 – 6

FIGURE 6 System Connection Diagrams

TXDg (18 17)

Differential 100K ECL data inputs This

is the NRZ or NRZI transmit data origi-

nating from the DP832515 Physical

Layer

Devices

(PLAYERTM)

the

DP832567VF or the DP83256VF-AP

Enhanced

Physical

Layer

Devices

(PLAYERa)

TXCg (13 14)

Differential 100K ECL clock inputs

This is the transmit clock generated by

the

National

Semiconductor

Clock

Distribution

Device

(CDDTM)

the

DP83257

the

DP83256VF-AP

Enhanced

Physical

Layer

Devices

(PLAYERa)

SCOg (19 20)

Differential 100K ECL data outputs

These outputs present the scrambled

transmit data to the PMD transmitter

DSCOg (27 26)

Differential 100K ECL outputs These

outputs present the descrambled data

back to the National Semiconductor

DP8325155 PLAYER the DP83256

7VF

DP83256VF-AP

devices

(PLAYERa)

RXCOg (24 25)

Differential 100K ECL clock outputs

These outputs supply a time aligned

version of RXCg (insuring proper set

and hold times relative to DSCOg)

the

National

Semiconductor

DP8325155 PLAYER the DP83256

7VF

DP83256VF-AP

devices

(PLAYERa) for clocking-in the final

descrambled data stream DSCOg

ENC0 1 (9 8)

TTL compatible inputs

These pins

work in conjunction with one another

to select different encoding schemes

or to place the DP83222 device into

transparent mode where no scram-

bling or encoding occurs Refer to Ta-

ble II for details of operation

CD (10)

TTL compatible input data This input

accepts the CD (Clock Detect) signal

from the receive Clock Recovery cir-

cuit if available If CD goes to a logic

low level due to insufficient data edg-

es for clock recovery the Stream Ci-

pher will switch to Sample mode in or-

der to restart the synchronization pro-

cess

SD (12)

Single-ended ECL data input This in-

put accepts the SDa signal from the

PMD If SD goes to a logic low level

due to loss of signal from the media

the DP83222 will switch to Sample

mode in order to restart the synchroni-

zation process

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