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DP83222 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83222
Description  CYCLONE Twisted Pair FDDI Stream Cipher Device
PDF  12 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83222 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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20 Pin Table
TABLE I Pinout Summary
Signal
Pin No
Description
Type
VCC
7 16 28
VCC
Supply
GND
1 4 11 15
GND
Supply Return
ECLVCC
21
ECLVCC
Supply
ECLGND
22
ECLGND
Supply Return
EXTVCC
23
External VCC
Supply
RXDg
3 2
Received Data from PMD Receiver
Diff 100K ECL In
RXCg
5 6
125 MHz Clock from Receiver PLL
Diff 100K ECL In
TXDg
18 17
Transmit Data from PHY PMRD
Diff 100K ECL In
TXCg
13 14
125 MHz Clock from PHY
Diff 100K ECL In
SCOg
19 20
Scrambled Data to PMD Transmitter
Diff ECL Out
DSCOg
27 26
Descrambled Data to PHY
Diff ECL Out
RXCOg
24 25
Realigned 125 MHz Clock to PHY
Diff ECL Out
ENC0
9
Encode 0
TTL Compatible CMOS In
ENC1
8
Encode 1
TTL Compatible CMOS In
CD
10
Clock Detect Input from Receive PLL
TTL Compatible CMOS In
SD
12
Signal Detect Input from PMD Receiver
Single-Ended ECL ln
30 Pin Definitions and Connection Diagrams
28-Pin PLCC
TLF11885 – 4
FIGURE 5 DP83222 Pinout
VCC (7 16 28)
Positive power supply for all internal
CMOS circuitry
The Stream Cipher
ScramblerDescrambler operates from
a single a5V DC power supply
GND (1 4 11 15)
Return path for internal CMOS circuitry
power supply
ECLVCC (21)
Positive power supply for all internal
ECL circuitry This power supply is in-
tentionally separated from others to re-
duce coupled supply noise
ECLGND (22)
Return path for all internal ECL circuit-
ry This Power supply return is inten-
tionally separated from others to re-
duce coupled supply noise
EXTVCC (23)
Positive power supply for emitter fol-
lower output circuitry
RXDg (3 2)
Differential 100K ECL data inputs
These inputs receive the ECL signals
generated by the National Semicon-
ductor DP83231 Clock Recovery De-
vice (CRDTM) or the DP832567VF-AP
Enhanced
Physical
Layer
Devices
(PLAYERaTM)
RXCg (5 6)
Differential 100K ECL clock inputs
These inputs receive the 125 MHz
clock regenerated by the National
Semiconductor DP83231 Clock Re-
covery Device (CRD) the DP83257VF
or
the
DP83256VF-AP
Enhanced
Physical Layer Devices (PLAYERa)
5



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