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DP83222 Datasheet(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83222
Description  CYCLONE Twisted Pair FDDI Stream Cipher Device
PDF  12 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83222 Datasheet(HTML) 8 Page - National Semiconductor (TI)

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44 AC ELECTRICAL CHARACTERISTICS
The AC Characteristics are specified over the operating range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T1
TXDTXC Setup Time
Refer to
Figure 8
10
ns
T2
TXDTXC Hold Time
Refer to
Figure 8
30
ns
T3
RXDRXC Setup Time
Refer to
Figure 9
30
ns
T4
RXDRXC Hold Time
Refer to
Figure 9
10
ns
T5
RXCODSCO Change Time
Refer to
Figure 10
05
30
ns
T6
RXCOa Pulse Width (High)
Refer to
Figure 10
40
60
ns
RXCOb Pulse Width (Low)
T7
Transition Time 20% – 80%
Refer to
Figure 11 (Note 1)
15
ns
T8
Transition Time 80% – 20%
Refer to
Figure 11 (Note 1)
15
ns
T9
Scrambler Data Valid TXCa
Refer to
Figure 12
to SCOa (Mode 1)
(Note 2) Table 2 (Includes
39
ns
Asynchronous Delay of 15 ns)
T9
Scrambler Data Valid TXCa
Refer to
Figure 12
to SCOa (Mode 2)
(Note 2) Table 2 (Includes
39
ns
Asynchronous Delay of 15 ns)
T9
Scrambler Data Valid TXCa
Refer to
Figure 12
to SCOa (Mode 3)
(Note 2) Table 2 (Includes
47
ns
Asynchronous Delay of 15 ns)
T9
Scrambler Data Valid TXCa
Refer to
Figure 12
to SCOa (Mode 4)
(Note 2) Table 2 (Includes
47
ns
Asynchronous Delay of 15 ns)
T10
Descrambler Data Valid RXCa
Refer to
Figure 13
to DSCOa (Mode 1)
(Note 2) Table 2 (Includes
231
ns
Asynchronous Delay of 15 ns)
T10
Descrambler Data Valid RXCa
Refer to
Figure 13
to DSCOa (Mode 2)
(Note 2) Table 2 (Includes
239
ns
Asynchronous Delay of 15 ns)
T10
Descrambler Data Valid RXCa
Refer to
Figure 13
to DSCOa (Mode 3)
(Note 2) Table 2 (Includes
239
ns
Asynchronous Delay of 15 ns)
T10
Descrambler Data Valid RXCa
Refer to
Figure 13
to DSCOa (Mode 4)
(Note 2) Table 2 (Includes
159
ns
Asynchronous Delay of 15 ns)
T10
Stream Cipher Hold Mode
From Receipt of First Valid Line
400
ns
Acquisition Time (Modes 1 2 3)
Symbol (Includes Async Delay of 15 ns)
T12
Clock Period
TXC e RXC (Note 3)
8
ns
T13
Total JitterScrambler
Referenced to TXCa (Note 1)
1
ns
T14
Total JitterDescrambler
Referenced to RXCOa (Note 1)
1
ns
Note 1
This parameter is not tested but is assured by correlation with characterization data
Note 2
Data Valid and Hold Acquisition timing specifications are based on Transmit and Receive clocks of 125 MHz (8 ns period) and include finite asynchronous
delay
Note 3
The DP83222 is FDDI compliant and will perform to specification over typical g50 ppm variation in clock frequency
8



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