TLF11885

August 1994

DP83222

CYCLONE

General Description

The

DP83222

CYCLONE

Stream

Cipher

Scrambler

Descrambler Device is an integrated circuit designed to in-

terface directly with the serial bit streams of a Twisted Pair

FDDI PMD The DP83222 is designed to be fully compatible

with the National Semiconductor FDDI Chip Sets including

DP83222 requires a 125 MHz Transmit Clock and corre-

sponding Receive Clock for synchronous data scrambling

and descrambling The DP83222 is compliant with the ANSI

X3T95 TP-PMD draft standard and is required for the re-

duction of EMI emission over unshielded media

The

DP83222 is specified to work in conjunction with existing

twisted pair transceiver signalling schemes such as MLT-3

or NRZI and enables high bandwidth transmission over

Twisted Pair copper media

Features

Y

Enables 100 Mbps FDDI signalling over Category 5

Unshielded Twisted Pair (UTP) cable and Type 1

Shielded Twisted Pair (STP)

Y

Reduces EMI emissions over Twisted Pair media

Y

Compatible with ANSI X3T95 TP-PMD Standard

Y

Y

Transparent mode of operation

Y

Flexible NRZ and NRZI format options

Y

Advanced BiCMOS process

Y

Signal Detect and Clock Detect inputs provided for en-

hanced functionality

Y

Suitable for Fiber Optic PMD replacement applications

Block Diagram

TLF11885 – 1

FIGURE 1 DP83222 Block Diagram

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A