TMPR4955AF datasheet(48/168 Pages) TOSHIBA

48 / 168 page

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Chapter 2 Features

2-4

Table 2.2.2 System Interface

PIN NAME

I / O

FUNCTION

SysAD(31:0)

I / O

System addres/data bus

A 32-bit address and data bus for communication between the processor and an external agent.

SysCmd(8:0)

I / O

System command/data identifier bus

A 9-bit bus for command and data identifier transmission between the processor and an external

agent.

SysADC(3:0)

I / O

System command/data check bus

A 4-bit bus containing parity check bits for the SysAD bus during data cycle.

SysCmdP

I / O

Reserved for system command/data identifier bus parity

For the TX4955A this signal is unused on input and zero on output.

ValidIn*

Valid input

The external agent asserts Validln* when it is driving a calid address or data on the SysAD bus and

valid command or data identifier on the SysCmd bus.

ValidOut*

Valid output

The processor asserts ValidOut* when it is driving a valid address or data on the SysAD bus and a

valid command or data identifier on the SysCmd bus.

ExtRqst*

External request

An external agent asserts ExtRqst* to request use of the System interface.

Release*

Release interface

Signals that the system interface needs to submit an external request.

WrRdy*

Write Ready

Signals that an external agent can now accept a processor write request.

RdRdy*

Read Ready

Signals that an external agent can now accept a processor read request.

Table 2.2.3 Clock/Control Interface

PIN NAME

I / O

FUNCTION

MasterClock

Master clock

Master clock input that establishes the processor operating frequency.

DivMode(1:0)

Set the operational frequency of the System interface

DivMode[1:0]

MasterClock

Pclock

41.8 MHz/50 MHz

167 MHz/200 MHz

66.7 MHz/80 MHz

167 MHz/200 MHz

83.5 MHz/100 MHz

167 MHz/200 MHz

55.7 MHz/66.7 MHz

167 MHz/200 MHz

TintDis

Timer-Interrupt disable input

0 enable Timer-Interrupt (Can not use Int 5*)

1 disable Timer-Interrupt (Can use Int 5*)

HALT/DOZE

HALT/DOZE mode output

This signal output the status of HALT or DOZE mode. This signal indicates that the TX4955A is in the

HALT or DOZE mode when this signal is “H”.

PLLReset*

PLL reset input

A signal to halt the PLL oscillation or the TX4955A built-in clock generator.

0 PLL is halt (no oscillation)

1 PLL is enabled.

Endian

Endianess input

Indicates the initial setting of the endian during a reset.

0 Little Endian

1 Big Endian

TMPR4955AF Datasheet(PDF) 48 Page - Toshiba Semiconductor

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