TMPR4955AF datasheet(58/168 Pages) TOSHIBA

58 / 168 page

Chapter 4 Clock Interface

4-2

4.2

Basic System Clocks

The various clock signals used in the TX4955A processor are described below, starting with

MasterClock

MasterClock, upon which the processor bases all internal and external clocking.

The clocks on the TX4955A processor are controlled by an on-processor Phase-locked Loop

(PLL) circuit. This circuit keeps the TX4955A processor’s internal clock edges aligned with the

clock edges of the MasterClock

MasterClock

MasterClock signal, which itself acts as the master system clock.

Inside the TX4955A processor, the MasterClock

MasterClock

MasterClock signal can be multiplied by a factor set by the

DivMode (1:0)

DivMode (1:0) inputs to the processor. All internal clocks are then derived from this clock. The

TX4955A processor has two primary internal clocks, the pipeline (also referred to as

processor)

clock, PClock

PClock

PClock, and the system interface clock, SClock

SClock

SClock. SClock

SClock

SClock has the same frequency and

phase as MasterClock

MasterClock

MasterClock.

4.2.1

MasterClock

The Processor bases all internal and external clocking on the single MasterClock

MasterClock

MasterClock input

signal. MasterClock

MasterClock

MasterClock specifications are shown in Figure 4.2.1.

tMCF

tMCR

tMCH

tMCL

tMCP

0.8VCC IO

0.2VCC IO

Figure 4.2.1 MasterClock

4.2.2

PClock

The pipeline (or

processor) clock, PClock

PClock

PClock, can be 2, 2.5, 3 or 4 times the MasterClock

MasterClock

frequency. This multiplication factor is determined by DivMode (1:0)

DivMode (1:0)

DivMode (1:0) pins, which are static

signal inputs to TX4955A.

All internal registers and latches use PClock

PClock

PClock.

4.2.3

SClock

The system interface clock, SClock

SClock

SClock, is the same as the MasterClock

MasterClock

MasterClock frequency. SClock

SClock

SClock is

always derived from Pclock.

Pclock.

Pclock. The TX4955A processor drives its outputs on this clock edge.

The first rising edge of SClock

SClock

SClock, after ColdReset

ColdReset

ColdReset* is deasserted, is aligned with the first

rising edge of MasterClock

MasterClock

MasterClock.

TMPR4955AF Datasheet(PDF) 58 Page - Toshiba Semiconductor

TMPR4955AF Datasheet(HTML) 58 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL