TMPR4955AF datasheet(69/168 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-9

5.9

Cache Testing

5.9.1

Cache disabling

The ICE# and DCE# bits in the Config register enable and disable the instruction and

data caches respectively.

When the cache is disabled, any attempt to access the cache causes a cache miss;

therefore, a cache refill does not occur. (A burst bus cycle does not occur, either, as is the

case with an access to a uncached memory space.) With the cache disabled, the Valid (V)

and Cache State (CS) bits for each entry remain unchanged.

Note: When the instruction cache is disabled

− All instruction fetches cause an instruction cache miss. External memory accesses

will occur as a single-read operation.

− Instruction cache operations by the CACHE instruction are valid.

Note: When the data cache is disabled

− All memory accesses by the load and store instructions cause a data cache miss. At

this time, no cache refill occurs. External memory accesses will occur as a

single-read or single-write operation.

− Data cache operations by the CACHE instruction are valid.

Note: How to disable the instruction cache reliably

− To disable the instruction cache, stop instruction streaming by following the

MTC0 instruction with a jump instruction, as shown below:

Example: MTC0 Rn, Config (Set ICE# bit.)

(Jump to L1 and stop streaming.)

NOP

(Jump delay slot)

L1: CACHE IndexInvalidate, offset (base)

5.9.2

Cache Flushing

Both the instruction and data caches are flushed by a Cold Reset or Warm Reset

exception. i:e., all the Valid and CS bits are cleared to zeroes.

The instruction cache is also flushed by the Index Invalidate and Hit Invalidate

operations with a CACHE instruction. The data cache is flushed by the Hit Invalidate

operation with a CACHE instruction.

Data is written back to the main memory when an Index Writeback Invalidate or Hit

Writeback Invalidate operation is performed, when a Hit Writeback operation is performed,

and when a cache line is replaced. When the write-back policy is employed, it is required to

consciously maintain cache coherency when flushing the cache.

TMPR4955AF Datasheet(PDF) 69 Page - Toshiba Semiconductor