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TMPR4955AF Datasheet(PDF) 77 Page - Toshiba Semiconductor

Part # TMPR4955AF
Description  64-Bit TX System RISC TX49 Family
PDF  168 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4955AF Datasheet(HTML) 77 Page - Toshiba Semiconductor

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Chapter 6 TX4955A System Interface
6-5
6.2.5.1
Master state and slave state
The system interface is placed in the master state when the TX4955A processor is
driving the SysAD bus and SysCmd bus. In contrast, the system interface is in the
slave state when the external agent is driving the SysAD bus and SysCmd bus.
The processor asserts the ValidOut* signal if the SysAD bus and SysCmd bus
become valid when the system interface is in the master state. The external agent
asserts the ValidIn* signal if the SysAD bus and SysCmd bus become valid when the
system interface is in the slave state.
6.2.5.2
Shifting from the master state to the slave state
The system interface remains in the master state unless it enters one of the
following states:
The external agent issues a request, then usage of the system interface is
granted (external arbitration).
The processor issues a read request and shifts into the slave mode by itself.
6.2.5.3
External arbitration
The external agent cannot issue external requests via the system interface unless
the system interface goes into the slave state. Shifts from the master state to the slave
state are arbitrated by the processor using the system interface handshake signals
ExtRqst* and Release.* This shift is performed as follows below.
1) The external agent sends notification that it would like to issue an external
request by asserting the ExtRqst* signal.
2) The processor releases the system interface and changes its state from the master
state to the slave state by asserting the Release* signal for 1 cycle.
3) The system interface returns to the master state when issuing of the external
request is complete.
6.2.5.4
Shifting to the slave state on its own
Shifting to the slave state on its own means that the shift from the master state to
the slave state is started by the processor when the processor read request is still on
hold. The Release signal is automatically asserted after the read transaction.
Self-invoked shifting to the slave state occurs either during the issue cycle of the read
request or several cycles after that.
After shifting to the slave state on its own, the processor returns to the master state
at the end of the next external request. This is made possible by a read request or
other type of external request.
The SysAd bus and SysCmd bus drives must start after the external agent confirms
that the processor autonomously shifted to the slave state. While the system interface
is in the slave state, the external agent can start making external requests without
requesting access to the system interface (without asserting the ExtRqst* signal).
The system interface returns to the master state when the external request ends.
If a processor read request is on hold after a read request is issued, the processor
automatically changes the system interface into the slave state even if the system
interface access necessary for the system agent to issue the external request has not
been requested. By shifting to the slave state in this manner, the external agent
becomes able to return read response data.



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